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参数资料
| 型号： | DS3112N |
| 厂商： | DALLAS SEMICONDUCTOR |
| 元件分类： | Digital Transmission Controller |
| 英文描述： | DATACOM, FRAMER, PBGA256 |
| 封装： | 27 X 27 MM, PLASTIC, BGA-256 |
| 文件页数： | 100/134页 |
| 文件大小： | 900K |
| 代理商： | DS3112N |
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DS3112
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Bits 0 to 6 / Remote Alarm Indication Signal Detected (RAIn when n = 1 to 7). This latched read
only alarm status bit will be set to a one each time the corresponding T2/E2/G747 framer detects an
incoming RAI alarm. This bit will be cleared when read unless the RAI alarm still exists in that
T2/E2/G747 framer. A change in state of the RAI in one or more of the T2/E2/G747 framers can cause
the T2E2SR2 status bit (in the MSR register) to be set and a hardware interrupt to occur if the IERAI bit
is set to a one and the T2E2SR2 bit in the Interrupt Mask for MSR (IMSR) register is set to a one.
See Figure 6.3B. The interrupt will be allowed to clear when this bit is read. The RAI alarm criteria is
described in Tables 6.3A, 6.3B and 6.3C. In the E3 Mode, RAI5 to RAI7 (bits 4 to 6) are meaningless
and should be ignored.
Bit 7 / Interrupt Enable for Remote Alarm Indication Signal (IERAI). This bit should be set to one if
the Host wishes to have RAI detection occurrences cause a hardware interrupt or the setting of the
T2E2SR2 status bit in the MSR register. See Figure 6.3B. The T2E2SR2 bit in the Interrupt Mask for the
Master Status Register (IMSR) must also be set to one for an interrupt to occur.
0 = interrupt masked
1 = interrupt unmasked
Bits 8 to 11 / E2 Receive National Bit (E2Snn when n = 1 to 4). This read only real time status bit
reports the incoming E2 National Bit (Sn). It is loaded at the start of each E2 frame as the Sn bit is
decoded. The Host can use the E2SOF status bit to determine when to read this bit. In the T3 and G747
Modes, this bit is meaningless and should be ignored. This bit cannot cause an interrupt to occur.
Bits 12 to 15 / E2 Receive Start Of Frame (E2SOFn where n = 1 to 4). This latched read only event
status bit will be set to a one on each E2 receive frame boundary. This bit will be cleared when read. The
setting of this status bit cannot cause an interrupt to occur.
T2E2SR2 Status Bit Flow Figure 6.3B
Note: All event and alarm latches above are cleared when the T2E2SR2 register is read.
Alarm Latch
Change in State Detect
RAI1
(T2E2SR2
Bit 0)
Internal RAI
Signal from
T2/E2 Framer 1
Alarm Latch
Change in State Detect
Internal RAI
Signal from
T2/E2 Framer 2
Alarm Latch
Change in State Detect
Internal RAI
Signal from
T2 Framer 7
OR
Mask
IERAI
(T2E2SR2
Bit 7)
RAI2
(T2E2SR2
Bit 1)
RAI7
(T2E2SR2
Bit 6)
Mask
T2E2SR2
(IMSR Bit 6)
INT*
Hardware
Signal
T2E2SR2
Status Bit
(MSR Bit 6)
Event Latch
相关PDF资料 |
PDF描述 |
|---|---|
| DS3112 | DATACOM, FRAMER, PBGA256 |
| DS3131 | SPECIALTY TELECOM CIRCUIT, PBGA256 |
| DS3134 | DATACOM, FRAMER, PBGA256 |
| DS3150QN | DATACOM, PCM TRANSCEIVER, PQCC28 |
| DS3150Q | DATACOM, PCM TRANSCEIVER, PQCC28 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| DS3112N+ | 功能描述:网络控制器与处理器 IC TEMPE T3/E3 MUX FRMR & M13/E13/G.747 MUX RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
| DS3112N+W | 功能描述:网络控制器与处理器 IC TEMPE T3/E3 MUX FRMR & M13/E13/G.747 MUX RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
| DS3112NC1 | 制造商:Maxim Integrated Products 功能描述:T3 E3 MULTIPLEXER, 3.3V T3/E3 FRAMER AND M13/E13/G.747 MUX - Rail/Tube |
| DS3112ND1E | 制造商:Rochester Electronics LLC 功能描述: 制造商:Maxim Integrated Products 功能描述: |
| DS3112RD | 功能描述:网络控制器与处理器 IC RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
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