参数资料
型号: DS3112N
厂商: DALLAS SEMICONDUCTOR
元件分类: Digital Transmission Controller
英文描述: DATACOM, FRAMER, PBGA256
封装: 27 X 27 MM, PLASTIC, BGA-256
文件页数: 13/134页
文件大小: 900K
代理商: DS3112N
DS3112
11 of 134
SECTION 2: SIGNAL DESCRIPTION
2.1 OVERVIEW / SIGNAL LEAD LIST
This section describes the input and output signals on the DS3112. Signal names follow a convention
that is shown in Table 2.1A. Table 2.1B lists all of the signals, their signal type, description, and lead
location. Symbols appended with an asterisks (*) are active low signals. The absence of an asterisks
implies an active high signal.
SIGNAL NAMING CONVENTION Table 2.1A
First Letters
Signal Category
Section
C
CPU / Host Control Access Port
2.2
FR
T3 / E3 Receive Framer
2.3
FT
T3 / E3 Transmit Formatter
2.4
LR
Low Speed (T1 or E1) Receive Port
2.5
LT
Low Speed (T1 or E1) Transmit Port
2.6
HR
High Speed (T3 or E3) Receive Port
2.7
HT
High Speed (T3 or E3) Transmit Port
2.8
J
JTAG Test Port
2.9
SIGNAL DESCRIPTION / LEAD LIST (preliminary lead assignment) Table 2.1B
Lead
Symbol
Type
Signal Description
C7
CALE
I
CPU Bus Address Latch Enable.
H3
CA0
I
CPU Bus Address Bit 0. LSB.
H2
CA1
I
CPU Bus Address Bit 1.
H1
CA2
I
CPU Bus Address Bit 2.
J4
CA3
I
CPU Bus Address Bit 3.
J3
CA4
I
CPU Bus Address Bit 4.
J2
CA5
I
CPU Bus Address Bit 5.
J1
CA6
I
CPU Bus Address Bit 6.
K2
CA7
I
CPU Bus Address Bit 7. MSB.
C4
CCS*
I
CPU Bus Chip Select.
C2
CD0
I/O
CPU Bus Data Bit 0. LSB.
D2
CD1
I/O
CPU Bus Data Bit 1.
D3
CD2
I/O
CPU Bus Data Bit 2.
E4
CD3
I/O
CPU Bus Data Bit 3.
C1
CD4
I/O
CPU Bus Data Bit 4.
D1
CD5
I/O
CPU Bus Data Bit 5.
E3
CD6
I/O
CPU Bus Data Bit 6.
E2
CD7
I/O
CPU Bus Data Bit 7.
E1
CD8
I/O
CPU Bus Data Bit 8.
F3
CD9
I/O
CPU Bus Data Bit 9.
G4
CD10
I/O
CPU Bus Data Bit 10.
F2
CD11
I/O
CPU Bus Data Bit 11.
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