参数资料
型号: DS3112N
厂商: DALLAS SEMICONDUCTOR
元件分类: Digital Transmission Controller
英文描述: DATACOM, FRAMER, PBGA256
封装: 27 X 27 MM, PLASTIC, BGA-256
文件页数: 130/134页
文件大小: 900K
代理商: DS3112N
DS3112
95 of 134
Note: When the CPU bus is operated in the 8-bit mode (CMS = 1), the Host should always write to the
lower byte (bits 0 to 7) first followed by the upper byte (bits 8 to 15).
Note: The THDLC is a write only register.
Note: The Transmit FIFO can be filled to a maximum capacity of 256 bytes. When the Transmit FIFO is
full, it will not accept any additional data.
Bits 0 to 7 / Transmit FIFO Data (D0 to D7). Data for the Transmit FIFO can be written to these bits.
D0 is the LSB and is transmitted first while D7 is the MSB and is transmitted last.
Bit 8 / Transmit Message End (TMEND). This bit is used to delineate multiple messages in the
Transmit FIFO. It should be set to a one when the last byte of a packet is written to the Transmit FIFO.
The setting of this bit indicates to the HDLC controller that the message is complete and that it should
calculate and add in the CRC checksum and at least two flags. This bit should be set to zero for all other
data written to the FIFO. All HDLC messages must be at least two bytes in length.
9.3 HDLC STATUS AND INTERRUPT REGISTER DESCRIPTION
Register Name:
HSR
Register Description:
HDLC Status Register
Register Address:
86h
Bit #
7
6
5
4
3210
Name
TUDR
RPE
RPS
RHWM
n/a
TLWM
n/a
TEND
Default
-
----
Bit #15
14
131211
10
9
8
Name
RABT
REMPTY
ROVR
TEMPTY
TFL3
TFL2
TFL1
TFL0
Default
-
---
-
Note: See Figure 9.3A for details on the signal flow for the status bits in the HSR register.
Note: Bits that are underlined are read only; all other bits are read-write.
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