参数资料
型号: DS3154N+
厂商: Maxim Integrated Products
文件页数: 32/61页
文件大小: 0K
描述: IC LIU DS3/E3/STS-1 QD 144CSBGA
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 160
类型: 线路接口装置(LIU)
驱动器/接收器数: 4/4
规程: IEEE 1149.1
电源电压: 3.135 V ~ 3.465 V
安装类型: 表面贴装
封装/外壳: 144-BGA,CSPBGA
供应商设备封装: 144-TECSBGA(13x13)
包装: 管件
DS3151/DS3152/DS3153/DS3154 Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs
38 of 61
Table 13-C. Framer Interface Timing
(VDD = 3.3V ±5%, TA = -40°C to +85°C.) (Figure 13-1 and Figure 13-2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
(Note 4)
22.4
(Note 5)
29.1
RCLK/TCLK Clock Period
t1
(Note 6)
19.3
ns
RCLK Duty Cycle
t2/t1, t3/t1
(Notes 7, 8)
45
50
55
%
TCLK Duty Cycle
t2/t1, t3/t1
(Note 8)
30
70
%
MCLK Duty Cycle
t2/t1, t3/t1
(Note 8)
30
70
%
TPOS/TDAT, TNEG to TCLK Setup
Time
t4
(Notes 8, 9)
2
ns
TPOS/TDAT, TNEG Hold Time
t5
(Notes 8, 9)
2
ns
RCLK to RPOS/RDAT, RNEG/RLCV,
and PRBS Value Change
t6
(Notes 7, 8, 10)
2
6
ns
RCLK Rise and Fall Time
t7
(Notes 8, 11)
5
ns
TCLK Rise and Fall Time
t8
(Notes 8, 12)
5
ns
Note 4: DS3 mode.
Note 5: E3 mode.
Note 6: STS-1 mode.
Note 7: Outputs loaded with 25pF, measured at 50% threshold.
Note 8: Not tested during production test.
Note 9: When TCINV = 0, TPOS/TDAT and TNEG are sampled on the rising edge of TCLK. When TCINV = 1, TPOS/TDAT and TNEG are
sampled on the falling edge of TCLK.
Note 10: When RCINV = 0, RPOS/RDAT and RNEG/RLCV are updated on the falling edge of RCLK. When RCINV = 1, RPOS/RDAT and
RNEG/RLCV are updated on the rising edge of RCLK.
Note 11: Outputs loaded with 25pF, measured between VOL (max) and VOH (min).
Note 12: Measured between VIL (max) and VIH (min).
Figure 13-1. Transmitter Framer Interface Timing Diagram
TCLK (INVERTED)
TPOS/TDAT,
TNEG
t4
t5
t1
t2
t3
TCLK (NORMAL)
t8
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