参数资料
| 型号： | DS33Z44+ |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 5/59页 |
| 文件大小： | 0K |
| 描述： | IC MAPPER ETHERNET 256CSBGA |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 40 |
| 应用： | 数据传输 |
| 接口： | 串行 |
| 电源电压： | 1.8V，2.5V，3.3V |
| 封装/外壳： | 256-LBGA，CSBGA |
| 供应商设备封装： | 256-CSBGA（17x17） |
| 包装： | 托盘 |
| 安装类型： | 表面贴装 |
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DS33Z44DK
13 of 59
CONFIGURATION SWITCHES AND JUMPERS
The DS33Z44DK has several configuration switches, banana plugs, oscillators, and jumpers. Table 2 provides a
description of these signals, given in order of appearance on the PC board (going from left to right, top to bottom).
Table 2. Main Board PC Board Configuration
BASIC SETTING
SILKSCREEN
REFERENCE
FUNCTION
SW MODE
HW MODE
DESCRIPTION
J25.9 + J25.10
Reserved
Not Installed
—
This jumper is not for use with the
DS33Z44 design kit. Pin J25.10 has
been removed to prevent accidental
installation.
J25.7 + J25.8
Enable device driver
User decision
—
When installed the device driver will
configure the DS33Z44 and the
Transceiver during power-up.
J25.5 + J25.6
Enable callbacks
User decision
—
When installed the driver will
respond to interrupts.
GROUND
(banana plug)
Power supply ground
—
System Ground. Always connected
to power supply.
VDD 3.3V
(banana plug)
Power supply VDD
—
System VDD. Always connected to
power supply.
OnCe
BDM
—
Debug connector for processor
DCEDTES
(3pos switch)
DS33Z44 mode pin;
DTE/DCE selection
Low
Low for DTE
RMIIMII
(3pos switch)
DS33Z44 mode pin
Low
High for RMII, low for MII
CKPHA
(3pos switch)
DS33Z44 mode pin
Low
SPI EEPROM hardware mode
configuration switch
MODEC0
(3pos switch)
DS33Z44 mode pin
High
Low
Software mode selected
MODEC1
(3pos switch)
DS33Z44 mode pin
Low
Software mode selected
HWMODE
(3pos switch)
DS33Z44 mode pin
Low
Hardware/software mode (software
mode selected)
SCANMO
(3pos switch)
DS33Z44 mode pin
Low
Set low for normal operation
SCANTRI
(3pos switch)
DS33Z44 mode pin
Low
Set low for normal operation
….testpoints….
DS33Z44 testpoints
—
Processor bus, JTAG and LAN side
testpoints for Zchip
Z-RESET (button) DS33Z44 reset
—
System reset
A2, A1, A0
(3pos switches)
DS33Z44/SPI pins
Mid position
Address pin/EEPROM config switch.
Set to mid position to allow
connection to processor.
SDRAM CLOCK
DS33Z44 SDRAM
clock
Installed
100MHz oscillator to drive SDRAM
clock
MII CLOCK
PHY MII clock
Installed
25MHz oscillator to drive SDRAM
clock
spi_cs, spi_ck,
spi_miso,
spi_mosi
—
SPI signals (for EEPROM memory)
….testpoints…..
DS33Z44 testpoints
—
DS33Z44 serial port testpoints
AFCS
(1 per port)
DS33Z44 mode pin
HW mode only
High
Set high to enable auto flow control.
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