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参数资料
| 型号： | DS4510U-5+T&R |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 7/12页 |
| 文件大小： | 0K |
| 描述： | IC SUPERVISOR W/NV MEM 10-USOP |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 3,000 |
| 类型： | 简单复位/加电复位 |
| 监视电压数目： | 1 |
| 输出： | 开路漏极或开路集电极 |
| 复位： | 低有效 |
| 复位超时： | 可调节/可选择 |
| 电压 - 阀值： | 4.625V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 10-TFSOP，10-MSOP（0.118"，3.00mm 宽） |
| 供应商设备封装： | 10-µMAX |
| 包装： | 带卷 (TR) |
CPU Supervisor with Nonvolatile Memory and
Programmable I/O
transistors. Read the I/O status register (F8h) to deter-
mine the logic levels present at the I/O pins.
t R
t F
User Memory
Three types of memory are present in the DS4510
(EEPROM, SEEPROM, and SRAM). The main user
V CCTP (MIN)
V CCTP (MAX)
V CCTP
t RPU
V CCTP (MAX)
V CCTP
V CCTP (MIN)
t RPD
memory is 64 bytes of EEPROM starting at address
00h. This memory is not SRAM shadowed, so all writes
to these locations result in EEPROM write cycles
regardless of the state of the SEE bit. Additional memo-
ry for storing application data includes 6 bytes of SRAM
(FAh–FFh), and 2 bytes of SEEPROM (F2h, F3h). Refer
to the register memory map ( Figure 3) for register
addresses and memory types. Figure 4 shows the bit
names for the memory-mapped I/O bytes and their fac-
tory default values.
The higher-order bits of the I/O registers that are not
V OH
V OL
Figure 1. CPU Supervisor Power-Up and Power-Down Timing
used, such as the four most significant bits of the
pullup-enable byte (address F0h), can be used as
additional memory. It is the responsibility of the appli-
cation to ensure that writes to these bytes do not
adversely affect bits controlling special functions of the
REGISTER ADDRESS (HEX)
F8
I/O STATUS
SRAM
MEMORY TYPE
DS4510.
REGISTER NAME
Figure 2. How to Read the Memory Map
00
USER BYTE
08
USER BYTE
10
USER BYTE
18
USER BYTE
20
USER BYTE
28
USER BYTE
30
USER BYTE
38
USER BYTE
40
EE 01
USER BYTE
EE 09
USER BYTE
EE 11
USER BYTE
EE 19
USER BYTE
EE 21
USER BYTE
EE 29
USER BYTE
EE 31
USER BYTE
EE 39
USER BYTE
41
EE 02
User byte
EE 0A
USER BYTE
EE 12
USER BYTE
EE 1A
USER BYTE
EE 22
USER BYTE
EE 2A
USER BYTE
EE 32
USER BYTE
EE 3A
USER BYTE
42
EE 03
USER BYTE
EE 0B
USER BYTE
EE 13
USER BYTE
EE 1B
USER BYTE
EE 23
USER BYTE
EE 2B
USER BYTE
EE 33
USER BYTE
EE 3B
USER BYTE
43
EE 04
USER BYTE
EE 0C
USER BYTE
EE 14
USER BYTE
EE 1C
USER BYTE
EE 24
USER BYTE
EE 2C
USER BYTE
EE 34
USER BYTE
EE 3C
USER BYTE
44
EE 05
USER BYTE
EE 0D
USER BYTE
EE 15
USER BYTE
EE 1D
USER BYTE
EE 25
USER BYTE
EE 2D
USER BYTE
EE 35
USER BYTE
EE 3D
USER BYTE
45
EE 06
USER BYTE
EE 0E
USER BYTE
EE 16
USER BYTE
EE 1E
USER BYTE
EE 26
USER BYTE
EE 2E
USER BYTE
EE 36
USER BYTE
EE 3E
USER BYTE
46
EE 07
USER BYTE
EE 0F
USER BYTE
EE 17
USER BYTE
EE 1F
USER BYTE
EE 27
USER BYTE
EE 2F
USER BYTE
EE 37
USER BYTE
EE 3F
USER BYTE
47
EE
EE
EE
EE
EE
EE
EE
EE
RESERVED
E8
E9 EA
EB
EC
ED
EE
EF
F0
SEE
F1
SEE F2
SEE F3
SEE F4
SEE
F5
SEE
F6
SEE
F7
SEE
PULLUP ENABLE
RESET DELAY
USER BYTE
USER BYTE
I/O 3 CONTROL
I/O 2 CONTROL
I/O 1 CONTROL
I/O 0 CONTROL
F8
SRAM
F9
SRAM FA
SRAM FB
SRAM FC
SRAM
FD
SRAM
FE
SRAM
FF
SRAM
I/O STATUS
CONFIG
USER BYTE
USER BYTE
USER BYTE
USER BYTE
USER BYTE
USER BYTE
*ITALICIZED BYTES HAVE BIT DESCRPTIONS, REFER TO FIGURE 3.
Figure 3. Register Memory Map
_____________________________________________________________________
7
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| DS4514FP000 | 制造商:Thomas & Betts 功能描述:400A,CON,4P5W,MG,514,3PY347V |
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