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| 型号： | DSP56858FVE |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 27/64页 |
| 文件大小： | 0K |
| 描述： | IC DSP 16BIT 120MHZ 144-LQFP |
| 标准包装： | 60 |
| 系列： | 568xx |
| 核心处理器： | 56800E |
| 芯体尺寸： | 16-位 |
| 速度： | 120MHz |
| 连通性： | EBI/EMI，SCI，SPI，SSI |
| 外围设备： | DMA，POR，WDT |
| 输入/输出数： | 47 |
| 程序存储器容量： | 80KB（40K x 16） |
| 程序存储器类型： | SRAM |
| RAM 容量： | 24K x 16 |
| 电压 - 电源 (Vcc/Vdd)： | 1.62 V ~ 1.98 V |
| 振荡器型： | 外部 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 144-LQFP |
| 包装： | 托盘 |
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Reset, Stop, Wait, Mode Select, and Interrupt Timing
56858 Technical Data, Rev. 6
Freescale Semiconductor
33
4.7 Reset, Stop, Wait, Mode Select, and Interrupt Timing
Table 4-8 Reset, Stop, Wait, Mode Select, and Interrupt Timing1, 2
Operating Conditions: VSS = VSSIO = VSSA = 0 V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0–3.6V, TA = –40° to +120°C, CL ≤ 50pF, fop = 120MHz
1. In the formulas, T = clock cycle. For fop = 120MHz operation and fipb = 60MHz, T = 8.33ns.
2. Parameters listed are guaranteed by design.
Characteristic
Symbol
Min
Max
Unit
See Figure
RESET Assertion to Address, Data and Control
Signals High Impedance
tRAZ
—11
ns
Minimum RESET Assertion Duration3
3. At reset, the PLL is disabled and bypassed. The part is then put into Run mode and tclk assumes the period of the source clock,
txtal, textal or tosc.
tRA
30
—
ns
RESET Deassertion to First External Address Output
tRDA
—
120T
ns
Edge-sensitive Interrupt Request Width
tIRW
1T + 3
—
ns
IRQA, IRQB Assertion to External Data Memory
Access Out Valid, caused by first instruction execution
in the interrupt service routine
tIDM
18T
—
ns
tIDM -FAST
14T
—
IRQA, IRQB Assertion to General Purpose Output
Valid, caused by first instruction execution in the
interrupt service routine
tIG
18T
—
ns
tIG -FAST
14T
—
IRQA Low to First Valid Interrupt Vector Address Out
recovery from Wait State4
4. The minimum is specified for the duration of an edge-sensitive IRQA interrupt required to recover from the Stop state. This is not
the minimum required so that the IRQA interrupt is accepted.
tIRI
22T
—
ns
tIRI -FAST
18T
—
Delay from IRQA Assertion (exiting Stop) to External
Data Memory5
5. The interrupt instruction fetch is visible on the pins only in Mode 3.
tIW
1.5T
—
ns
Delay from IRQA Assertion (exiting Wait) to External
Data Memory
Fast6
Normal7
6. Fast stop mode:
Fast stop recovery applies when external clocking is in use (direct clocking to XTAL) or when fast stop mode recovery is
requested (OMR bit 6 is set to 1). In both cases the PLL and the master clock are unaffected by stop mode entry. Recovery takes
one less cycle and tclk will continue same value it had before stop mode was entered.
tIF
18T
22ET
—
ns
RSTO pulse width8
normal operation
internal reset mode
tRSTO
128ET
8ET
—
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