参数资料
型号: DSP56858FVE
厂商: Freescale Semiconductor
文件页数: 62/64页
文件大小: 0K
描述: IC DSP 16BIT 120MHZ 144-LQFP
标准包装: 60
系列: 568xx
核心处理器: 56800E
芯体尺寸: 16-位
速度: 120MHz
连通性: EBI/EMI,SCI,SPI,SSI
外围设备: DMA,POR,WDT
输入/输出数: 47
程序存储器容量: 80KB(40K x 16)
程序存储器类型: SRAM
RAM 容量: 24K x 16
电压 - 电源 (Vcc/Vdd): 1.62 V ~ 1.98 V
振荡器型: 外部
工作温度: -40°C ~ 85°C
封装/外壳: 144-LQFP
包装: 托盘
Introduction
56858 Technical Data, Rev. 6
Freescale Semiconductor
7
Part 2 Signal/Connection Descriptions
2.1 Introduction
The input and output signals of the 56858 are organized into functional groups, as shown in Table 2-1 and
as illustrated in Figure 2-1. In Table 3-1 each table row describes the package pin and the signal or signals
present.
1. VDD = VDD CORE, VSS = VSS CORE, VDDIO= VDD IO, VSSIO = VSS IO, VDDA = VDD ANA, VSSA = VSS ANA
2. MODA, MODB and MODC can be used as GPIO after the bootstrap process has completed.
3. The following Host Interface signals are multiplexed: HRWB to HRD, HDS to HWR, HREQ to HTRQ and HACK to HRRQ.
Table 2-1 56858 Functional Group Pin Allocations
Functional Group
Number of Pins
Power (VDD, VDDIO, or VDDA)
(8, 12, 1)1
Ground (VSS, VSSIO,or VSSA)
(8, 14, 2)1
PLL and Clock
3
External Bus Signals
39
External Chip Select*
4
Interrupt and Program Control
72
Host Interface (HI)*
163
Enhanced Synchronous Serial Interface (ESSI0) Port*
6
Enhanced Synchronous Serial Interface (ESSI1) Port*
6
Serial Communications Interface (SCI0) Ports*
2
Serial Communications Interface (SCI1) Ports*
2
Serial Peripheral Interface (SPI) Port*
4
Quad Timer Module Port*
4
JTAG/On-Chip Emulation (OnCE)
6
*Alternately, GPIO pins
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