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参数资料
| 型号： | DSPAUDIOEVMMB1E |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 11/60页 |
| 文件大小： | 0K |
| 描述： | BOARD MOTHER DSP563XX |
| 标准包装： | 1 |
| 系列： | Symphony™ |
| 类型： | DSP |
| 适用于相关产品： | DSP563XX |
| 所含物品： | 主板 |
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Signal Headers
2.2.4.5
JP10 – Config / Debug MPU Communication
The JP10 jumpers provide a communication port between the debug microcontroller and the configuration microcontroller. When the SDI
debugger is used and the AUX5 jumper is out, the SDI debugger interface controls the audio input source. The JP10 jumpers provide a
communication port between the debug microcontroller and the configuration microcontroller. When the SDI debugger is used, and the AUX5
jumper is out, the SDI debugger interface controls the audio input source. To allow this, all JP10 jumpers should be populated.
2.2.4.6
JP11 – AUX Mode Input Source Selection
The JP11 jumpers are present as an alternative to using the SDI debugger software to select between the various inputs available. If the AUX5
jumper is present then the following jumper settings will result in the input selection shown in Table 2-5
Table 2-5. JP11 Selections
Input Selected
RX1
RX2
RX3
RX4
AIN1
SDI
Aux5
1
1
1
1
1
0
Aux4*
0
0
0
0
0
X
Aux3
0
0
0
0
1
X
Aux2
0
0
1
1
0
X
Aux1
0
1
0
1
0
X
debugger
selects input
* When the Aux5 jumper is present, the Aux4 jumper directly
controls the mute functionality of the EVM motherboard.
2.3
Signal Headers
These headers allow for external debugger connections, analog output signal measurement, and GPIO access.
2.3.1
P1 — PPI Header
The PPI header connections are to allow for backwards compatibility with existing PPI software tool set and to allow easy access to the SHI
port connections from the motherboard. Note that when using PPI source, JP8 must have PPI Port jumper in place.
Table 2-6. P1 — PPI Header
2.3.2
NC(1)
GND
GND
SDA
VDD
P2 — OnCE Header
*
*
*
*
*
*
*
*
*
*
SS/HA2
SCK/SCL
HREQ
MOSI / HA0
MISO
The P2 OnCE header is for connection of an external OnCE/JTAG debugger tool to the OnCE/JTAG port of the DSP on the daughterboard.
Further explanation of the OnCE/JTAG signal definition can be found in the DSP users guides. The P2 OnCE header is for connection of an
external OnCE/JTAG debugger tool to the OnCE/JTAG port of the DSP on the daughterboard. Further explanation of the OnCE/JTAG signal
definition can be found in the DSP users guides. Note that when using an external OnCE/JTAG debugger tool, the JP9 JTAG jumper should
be in the "OnCE" position.
DSPAUDIOEVM Users Guide, Rev. 2.4
This document contains information on a new product. Specifications and information herein are subject ot change without notice.
Freescale Semiconductor
5
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