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| 型号： | DSPAUDIOEVMMB1E |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 18/60页 |
| 文件大小： | 0K |
| 描述： | BOARD MOTHER DSP563XX |
| 标准包装： | 1 |
| 系列： | Symphony™ |
| 类型： | DSP |
| 适用于相关产品： | DSP563XX |
| 所含物品： | 主板 |
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Daughterboard Audio I / O and Clock Control Header
4.5
Daughterboard Audio I / O and Clock Control Header
Table 4-2. Daughterboard Audio I/O and clock Control Header
*
*
A
*
*
B
*
*
C
*
*
D
*
*
E
*
*
F
*
*
G
*
*
H
*
*
I
*
*
J
*
*
K
*
*
L
*
*
M
*
*
N
*
*
O
*
*
P
*
*
Q
*
*
R
*
*
S
*
*
T
*
*
U
JP3
JP4
JP5 JP6 JP7
JP8
JP9
JP10
JP11
JP12
JP13
JP14
4.5.1
JP3 - Synchronous/Asynchronous Clock Control
This jumper set controls whether or not the DSP is in synchronous or asynchronous mode. Position A allows the DSP GPIO (pin PB1) to
choose the mode. Position B forces the mode to be asynchronous, and no jumper forces synchronous mode. In synchronous mode FST is
connected to FSR, and SCKT is connected to SCKR on the ESAI port of the DSP.
4.5.2
JP4 – Single/Double Speed Clocking Control
This jumper set controls whether or not the motherboard is in single or double speed mode. Position C forces the motherboard into double
speed mode. Position D allows the DSP GPIO pin PE10 to control the mode (e.g., through a PPP), and no jumper forces single speed mode.
An example of this signal’s use is for decoding of DTS 96/24 content. In this mode, it is required to update the masterclock ration expectation
in the D/A converters and S/PDIF transmitters because the DTS 96/24 decoder doubles the audio sample rate as part of the decoding process.
4.5.3
JP5 - DSP MUTE Control
This jumper controls the mute signal when used in conjunction with the Software Architecture or GPIO control. With the jumper in place, the
mute control is connected to the DSP GPIO pin PE11. No jumper means that mute functionality will only be controlled by the motherboard.
4.5.4
JP6 - FSR_1 Connection
This jumper connects/shorts the FSR and FSR_1 signals together. No jumper means that the FSR_1 signal stops at header P1.
4.5.5
JP7 - SCKR_1 Connection
This jumper connects/shorts the SCKR and SCKR_1 signals together. No jumper means that the SCKR_1 signal stops at header P1.
4.5.6
JP8 - SCKT_1 Connection
This set of jumpers determines which serial clock source is used for the AKM DAC4_6. Position I directs the ESAI_0 SCKT signal to
DAC4_6, position H directs the ESAI_1 SCKT signal to DAC4_6 and population of both jumpers will synchronize/short the two ESAI port
SCKT lines.
4.5.7
JP9 - FST_1 Connection
This set of jumpers determines which frame sync clock source is used for the AKM DAC4_6. The K position directs the ESAI FST signal to
DAC4_6. Position J directs the ESAI_1 FST signal to DAC4_6, and population of both jumpers will synchronize/short the two ESAI port
FST lines.
4.5.8
JP10 - SDO5/SDI0 Configuration
This jumper set controls the signal connections of SDO5/SDI0. Depending on the ESAI setting in the DSP, this pin can be configured as an
input or an output. A jumper in position L feeds the SDI0 signal from the ADC2 microphone source. A jumper in the M position feeds the
SDO5 signal to DAC4_6.
DSPAUDIOEVM Users Guide, Rev. 2.4
This document contains information on a new product. Specifications and information herein are subject ot change without notice.
12
Freescale Semiconductor
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