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参数资料
| 型号： | DSPAUDIOEVMMB1E |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 22/60页 |
| 文件大小： | 0K |
| 描述： | BOARD MOTHER DSP563XX |
| 标准包装： | 1 |
| 系列： | Symphony™ |
| 类型： | DSP |
| 适用于相关产品： | DSP563XX |
| 所含物品： | 主板 |
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Daughterboard Audio I/O and Clock Control Header
5.5.9
JP9 – FST/FST_1 Selection
This jumper set determines which frame sync clock source is used for DAC4-6. A jumper in position O directs the ESAI FST signal to
DAC4-6. A jumper in position N directs the ESAI_1 FST signal to DAC4-6. If both jumpers are placed this will connect/short the FST and
FST_1 signals together.
5.5.10
JP10 – SCKT/SCKT_1 Selection
This jumper pair controls which serial clock source is used for DAC4-6. A jumper in position Q directs the ESAI SCKT signal to DAC4-6.
A jumper in position P directs the ESAI_1 SCKT signal to DAC4-6. If both jumpers are placed this will connect/short the SCKT and SCKT_1
signals together.
5.5.11
JP11 – DSP Mute Control
This jumper controls the mute signal when used in conjunction with the Software Architecture or GPIO control. With the jumper in place the
mute control is connected to the DSP GPIO (pinPG5). No jumper means that the mute functionality will only be controlled by the
motherboard.
5.5.12
JP13 – I2C Boot ROM Enable
This set of jumpers allows the on-board serial EEPROM to be removed from the SHI bus. Jumper location W connects the serial data line to
the DSP MISO signal and location X connects the serial clock line to the DSP SCK signal. Both jumpers must be placed to use bootstrap
modes 9 or B.
5.5.13
JP14 – S/PDIF Lock Control
This jumper is designed for future compatibility. For proper operation a jumper should be placed in position U.
5.5.14
JP15 – Master Clock Control
This jumper pair allows the DSP to supply a master transmit clock from either ESAI port via the HCKT signal. A jumper in position S sources
the transmit master clock from the AKM 4114 S/PDIF receiver, while a jumper in position T sources the transmit master clock from either
HCKT or HCKT_1 (these signals are connected/shorted together in either jumper position).
5.5.15
P1 – ESAI Receive In
This header allows for external connections to ESAI and ESAI_1 receiver signals and GPIO. The odd row is ground while the even row of
pins is signal. This provides ground isolation between each signal when used with ribbon cable connectors.
5.5.16
P2 – ESAI Transmit Out
This header allows for external connections to ESAI and ESAI_1 transmitter signals and GPIO. The odd row is ground while the even row of
pins is signal. This provides ground isolation between each signal when used with ribbon cable connectors.
DSPAUDIOEVM Users Guide, Rev. 2.4
This document contains information on a new product. Specifications and information herein are subject ot change without notice.
16
Freescale Semiconductor
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