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参数资料
型号： DSPIC30F2011-20I/P
厂商： Microchip Technology
文件页数： 10/66页
文件大小： 0K
描述： IC DSPIC MCU/DSP 12K 18DIP
产品培训模块： Serial Communications using dsPIC30F I2C
Serial Communications using dsPIC30F SPI
Serial Communications using dsPIC30F UART
dsPIC30F 12 bit ADC - Part 2
dsPIC30F Addressing Modes - Part 1
dsPIC30F Architecture - Part 1
dsPIC30F DSP Engine & ALU
dsPIC30F Interrupts
dsPIC30F Motor Control PWM
dsPIC Timers
Asynchronous Stimulus
dsPIC30F Addressing Modes - Part 2
dsPIC30F Architecture - Part 2
dsPIC30F 12-bit ADC Part 1
标准包装： 25
系列： dsPIC™ 30F
核心处理器： dsPIC
芯体尺寸： 16-位
速度： 20 MIPS
连通性： I²C，SPI，UART/USART
外围设备： 欠压检测/复位，POR，PWM，WDT
输入/输出数： 12
程序存储器容量： 12KB（4K x 24）
程序存储器类型： 闪存
RAM 容量： 1K x 8
电压 - 电源 (Vcc/Vdd)： 2.5 V ~ 5.5 V
数据转换器： A/D 8x12b
振荡器型： 内部
工作温度： -40°C ~ 85°C
封装/外壳： 18-DIP（0.300"，7.62mm）
包装： 管件
配用： AC30F005-ND - MODULE SCKT DSPIC30F 18DIP/SOIC
ACICE0202-ND - ADAPTER MPLABICE 18P 300 MIL
其它名称： DSPIC30F2011-20IP
dsPIC30F Flash Programming Specification
DS70102K-page 18
2010 Microchip Technology Inc.
5.7.2
PROGRAMMING METHODOLOGY
System operation Configuration bits are inherently
different than all other memory cells. Unlike code
memory,
data
EEPROM
and
code-protect
Configuration bits, the system operation bits cannot be
erased. If the chip is erased with the ERASEB
command, the system-operation bits retain their
previous value. Consequently, you should make no
assumption about the value of the system operation
bits. They should always be programmed to their
desired setting.
Configuration bits are programmed as a single word at
a time using the PROGC command. The PROGC
command specifies the configuration data and
Configuration register address. When Configuration
bits are programmed, any unimplemented bits must be
programmed with a ‘0’, and any reserved bits must be
programmed with a ‘1’.
Four PROGC commands are required to program all the
Configuration bits. Figure 5-5 illustrates the flowchart of
Configuration bit programming.
Note:
If the General Code Segment Code
Protect (GCP) bit is programmed to ‘0’,
code memory is code-protected and can-
not be read. Code memory must
be verified before enabling read protec-
tion. See Section 5.7.4 “Code-Protect
Configuration Bits” for more information
about code-protect Configuration bits.
5.7.3
PROGRAMMING VERIFICATION
Once the Configuration bits are programmed, the
contents of memory should be verified to ensure that
the programming was successful. Verification requires
the Configuration bits to be read back and compared
against the copy held in the programmer’s buffer. The
READD command reads back the programmed
Configuration
bits
and
verifies
whether
the
programming was successful.
Any unimplemented Configuration bits are read-only
and read as ‘0’.
5.7.4
CODE-PROTECT CONFIGURATION
BITS
The FBS, FSS and FGS Configuration registers are
special Configuration registers that control the size and
level of code protection for the Boot Segment, Secure
Segment and General Segment, respectively. For each
segment, two main forms of code protection are
provided. One form prevents code memory from being
written (write protection), while the other prevents code
memory from being read (read protection).
The BWRP, SWRP and GWRP bits control write
protection; and BSS<2:0>, SSS<2:0> and GSS<1:0>
bits control read protection. The Chip Erase ERASEB
command sets all the code protection bits to ‘1’, which
allows the device to be programmed.
When write protection is enabled, any programming
operation to code memory will fail. When read
protection is enabled, any read from code memory will
cause a ‘0x0’ to be read, regardless of the actual
contents of code memory. Since the programming
executive always verifies what it programs, attempting
to program code memory with read protection enabled
will also result in failure.
It is imperative that all code protection bits are ‘1’ while
the device is being programmed and verified. Only after
the device is programmed and verified should any of
the above bits be programmed to ‘0’ (see Section 5.7
“Configuration Bits Programming”).
In addition to code memory protection, parts of data
EEPROM and/or data RAM can be configured to be
accessible only by code resident in the Boot Segment
and/or Secure Segment. The sizes of these “reserved”
sections are user-configurable, using the EBS,
RBS<1:0>, ESS<1:0> and RSS<1:0> bits.
Note 1: All bits in the FBS, FSS and FGS
Configuration registers can only be
programmed to a value of ‘0’. ERASEB is
the only way to reprogram code-protect
bits from ON (‘0’) to OFF (‘1’).
2: If any of the code-protect bits in FBS,
FSS, or FGS are clear, the entire device
must be erased before it can be
reprogrammed.
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相关代理商/技术参数
参数描述
dsPIC30F2011-30I/ML 功能描述:数字信号处理器和控制器 - DSP, DSC 28LD 30MIPS 12 KB RoHS:否 制造商:Microchip Technology 核心:dsPIC 数据总线宽度:16 bit 程序存储器大小:16 KB 数据 RAM 大小:2 KB 最大时钟频率:40 MHz 可编程输入/输出端数量:35 定时器数量:3 设备每秒兆指令数:50 MIPs 工作电源电压:3.3 V 最大工作温度:+ 85 C 封装 / 箱体:TQFP-44 安装风格:SMD/SMT
dsPIC30F2011-30I/P 功能描述:数字信号处理器和控制器 - DSP, DSC 18LD 30MIPS 12 KB RoHS:否 制造商:Microchip Technology 核心:dsPIC 数据总线宽度:16 bit 程序存储器大小:16 KB 数据 RAM 大小:2 KB 最大时钟频率:40 MHz 可编程输入/输出端数量:35 定时器数量:3 设备每秒兆指令数:50 MIPs 工作电源电压:3.3 V 最大工作温度:+ 85 C 封装 / 箱体:TQFP-44 安装风格:SMD/SMT
DSPIC30F2011-30I/P 制造商:Microchip Technology Inc 功能描述:16- Bit Digital Signal Controller
dsPIC30F2011-30I/SO 功能描述:数字信号处理器和控制器 - DSP, DSC 18LD 30MIPS 12 KB RoHS:否 制造商:Microchip Technology 核心:dsPIC 数据总线宽度:16 bit 程序存储器大小:16 KB 数据 RAM 大小:2 KB 最大时钟频率:40 MHz 可编程输入/输出端数量:35 定时器数量:3 设备每秒兆指令数:50 MIPs 工作电源电压:3.3 V 最大工作温度:+ 85 C 封装 / 箱体:TQFP-44 安装风格:SMD/SMT
DSPIC30F2011-30I/SO 制造商:Microchip Technology Inc 功能描述:16- Bit Digital Signal Controller
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