- 您现在的位置：买卖IC网 > PDF目录11486 > DSPIC30F2011-20I/P (Microchip Technology)IC DSPIC MCU/DSP 12K 18DIP PDF资料下载
参数资料
| 型号： | DSPIC30F2011-20I/P |
| 厂商： | Microchip Technology |
| 文件页数： | 28/66页 |
| 文件大小： | 0K |
| 描述： | IC DSPIC MCU/DSP 12K 18DIP |
| 产品培训模块： | Serial Communications using dsPIC30F I2C Serial Communications using dsPIC30F SPI Serial Communications using dsPIC30F UART dsPIC30F 12 bit ADC - Part 2 dsPIC30F Addressing Modes - Part 1 dsPIC30F Architecture - Part 1 dsPIC30F DSP Engine & ALU dsPIC30F Interrupts dsPIC30F Motor Control PWM dsPIC Timers Asynchronous Stimulus dsPIC30F Addressing Modes - Part 2 dsPIC30F Architecture - Part 2 dsPIC30F 12-bit ADC Part 1 |
| 标准包装： | 25 |
| 系列： | dsPIC™ 30F |
| 核心处理器： | dsPIC |
| 芯体尺寸： | 16-位 |
| 速度： | 20 MIPS |
| 连通性： | I²C，SPI，UART/USART |
| 外围设备： | 欠压检测/复位，POR，PWM，WDT |
| 输入/输出数： | 12 |
| 程序存储器容量： | 12KB（4K x 24） |
| 程序存储器类型： | 闪存 |
| RAM 容量： | 1K x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 2.5 V ~ 5.5 V |
| 数据转换器： | A/D 8x12b |
| 振荡器型： | 内部 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 18-DIP（0.300"，7.62mm） |
| 包装： | 管件 |
| 配用： | AC30F005-ND - MODULE SCKT DSPIC30F 18DIP/SOIC ACICE0202-ND - ADAPTER MPLABICE 18P 300 MIL |
| 其它名称： | DSPIC30F2011-20IP |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页当前第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页
dsPIC30F Flash Programming Specification
DS70102K-page 34
2010 Microchip Technology Inc.
11.0 ICSP MODE
11.1
ICSP Mode
ICSP mode is a special programming protocol that
allows you to read and write to the dsPIC30F program-
ming executive. The ICSP mode is the second (and
slower) method used to program the device. This mode
also has the ability to read the contents of executive
memory to determine whether the programming exec-
utive is present. This capability is accomplished by
applying control codes and instructions serially to the
device using pins PGC and PGD.
In ICSP mode, the system clock is taken from the PGC
pin, regardless of the device’s oscillator Configuration
bits. All instructions are first shifted serially into an
internal buffer, then loaded into the Instruction register
and executed. No program fetching occurs from
internal memory. Instructions are fed in 24 bits at a
time. PGD is used to shift data in and PGC is used as
both the serial shift clock and the CPU execution clock.
Data is transmitted on the rising edge and latched on
the falling edge of PGC. For all data transmissions, the
Least Significant bit (LSb) is transmitted first.
11.2
ICSP Operation
Upon entry into ICSP mode, the CPU is idle. Execution
of the CPU is governed by an internal state machine. A
4-bit control code is clocked in using PGC and PGD,
and this control code is used to command the CPU
(see Table 11-1).
The SIX control code is used to send instructions to the
CPU for execution, while the REGOUT control code is
used to read data out of the device via the VISI register.
The operation details of ICSP mode are provided in
TABLE 11-1:
CPU CONTROL CODES IN
ICSP MODE
4-bit
Control
Code
Mnemonic
Description
0000b
SIX
Shift in 24-bit instruction
and execute.
0001b
REGOUT
Shift out the VISI
register.
0010b-1111b N/A
Reserved.
11.2.1
SIX SERIAL INSTRUCTION
EXECUTION
The SIX control code allows execution of dsPIC30F
assembly instructions. When the SIX code is received,
the CPU is suspended for 24 clock cycles as the
instruction is then clocked into the internal buffer. Once
the instruction is shifted in, the state machine allows it
to be executed over the next four clock cycles. While
the received instruction is executed, the state machine
simultaneously shifts in the next 4-bit command (see
Note 1: During ICSP operation, the operating
frequency of PGC must not exceed
5 MHz.
2: Because ICSP is slower, it is recom-
mended that only Enhanced ICSP (E-
ICSP) mode be used for device program-
ming, as described in Section 5.1
Note 1: Coming out of the ICSP entry sequence,
the first 4-bit control code is always
forced to SIX and a forced NOP instruc-
tion is executed by the CPU. Five addi-
tional PGC clocks are needed on start-
up, thereby resulting in a 9-bit SIX com-
mand instead of the normal 4-bit SIX
command. After the forced SIX is clocked
in, ICSP operation resumes as normal
(the next 24 clock cycles load the first
instruction word to the CPU). See
Figure 11-1 for details.
2: TBLRDH, TBLRDL, TBLWTH and TBLWTL
instructions must be followed by a NOP
instruction.
相关PDF资料 |
PDF描述 |
|---|---|
| ADV3220ACPZ | IC MULTIPLEXER 2:1 16LFCSP |
| GRM319F51E105ZA01D | CAP CER 1UF 25V Y5V 1206 |
| ADV3219ACPZ | IC MULTIPLEXER 2:1 16LFCSP |
| GRM2197U2A4R7CD01D | CAP CER 4.7PF 100V U2J 0805 |
| ADG636YRUZ | IC SWITCH DUAL SPDT 14TSSOP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| dsPIC30F2011-30I/ML | 功能描述:数字信号处理器和控制器 - DSP, DSC 28LD 30MIPS 12 KB RoHS:否 制造商:Microchip Technology 核心:dsPIC 数据总线宽度:16 bit 程序存储器大小:16 KB 数据 RAM 大小:2 KB 最大时钟频率:40 MHz 可编程输入/输出端数量:35 定时器数量:3 设备每秒兆指令数:50 MIPs 工作电源电压:3.3 V 最大工作温度:+ 85 C 封装 / 箱体:TQFP-44 安装风格:SMD/SMT |
| dsPIC30F2011-30I/P | 功能描述:数字信号处理器和控制器 - DSP, DSC 18LD 30MIPS 12 KB RoHS:否 制造商:Microchip Technology 核心:dsPIC 数据总线宽度:16 bit 程序存储器大小:16 KB 数据 RAM 大小:2 KB 最大时钟频率:40 MHz 可编程输入/输出端数量:35 定时器数量:3 设备每秒兆指令数:50 MIPs 工作电源电压:3.3 V 最大工作温度:+ 85 C 封装 / 箱体:TQFP-44 安装风格:SMD/SMT |
| DSPIC30F2011-30I/P | 制造商:Microchip Technology Inc 功能描述:16- Bit Digital Signal Controller |
| dsPIC30F2011-30I/SO | 功能描述:数字信号处理器和控制器 - DSP, DSC 18LD 30MIPS 12 KB RoHS:否 制造商:Microchip Technology 核心:dsPIC 数据总线宽度:16 bit 程序存储器大小:16 KB 数据 RAM 大小:2 KB 最大时钟频率:40 MHz 可编程输入/输出端数量:35 定时器数量:3 设备每秒兆指令数:50 MIPs 工作电源电压:3.3 V 最大工作温度:+ 85 C 封装 / 箱体:TQFP-44 安装风格:SMD/SMT |
| DSPIC30F2011-30I/SO | 制造商:Microchip Technology Inc 功能描述:16- Bit Digital Signal Controller |
发布紧急采购，3分钟左右您将得到回复。