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参数资料
| 型号： | DSPIC30F2012-30I/ML |
| 厂商： | Microchip Technology |
| 文件页数： | 28/66页 |
| 文件大小： | 0K |
| 描述： | IC DSPIC MCU/DSP 12K 28QFN |
| 产品培训模块： | Serial Communications using dsPIC30F I2C Serial Communications using dsPIC30F SPI Serial Communications using dsPIC30F UART dsPIC30F 12 bit ADC - Part 2 dsPIC30F Addressing Modes - Part 1 dsPIC30F Architecture - Part 1 dsPIC30F DSP Engine & ALU dsPIC30F Interrupts dsPIC30F Motor Control PWM dsPIC Timers Asynchronous Stimulus dsPIC30F Addressing Modes - Part 2 dsPIC30F Architecture - Part 2 dsPIC30F 12-bit ADC Part 1 |
| 标准包装： | 61 |
| 系列： | dsPIC™ 30F |
| 核心处理器： | dsPIC |
| 芯体尺寸： | 16-位 |
| 速度： | 30 MIP |
| 连通性： | I²C，SPI，UART/USART |
| 外围设备： | 欠压检测/复位，POR，PWM，WDT |
| 输入/输出数： | 20 |
| 程序存储器容量： | 12KB（4K x 24） |
| 程序存储器类型： | 闪存 |
| RAM 容量： | 1K x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 2.5 V ~ 5.5 V |
| 数据转换器： | A/D 10x12b |
| 振荡器型： | 内部 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 28-VQFN 裸露焊盘 |
| 包装： | 管件 |
| 产品目录页面： | 650 (CN2011-ZH PDF) |
| 配用： | AC164322-ND - MODULE SOCKET MPLAB PM3 28/44QFN DV164005-ND - KIT ICD2 SIMPLE SUIT W/USB CABLE |
| 其它名称： | DSPIC30F201230IML |
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dsPIC30F Flash Programming Specification
DS70102K-page 34
2010 Microchip Technology Inc.
11.0 ICSP MODE
11.1
ICSP Mode
ICSP mode is a special programming protocol that
allows you to read and write to the dsPIC30F program-
ming executive. The ICSP mode is the second (and
slower) method used to program the device. This mode
also has the ability to read the contents of executive
memory to determine whether the programming exec-
utive is present. This capability is accomplished by
applying control codes and instructions serially to the
device using pins PGC and PGD.
In ICSP mode, the system clock is taken from the PGC
pin, regardless of the device’s oscillator Configuration
bits. All instructions are first shifted serially into an
internal buffer, then loaded into the Instruction register
and executed. No program fetching occurs from
internal memory. Instructions are fed in 24 bits at a
time. PGD is used to shift data in and PGC is used as
both the serial shift clock and the CPU execution clock.
Data is transmitted on the rising edge and latched on
the falling edge of PGC. For all data transmissions, the
Least Significant bit (LSb) is transmitted first.
11.2
ICSP Operation
Upon entry into ICSP mode, the CPU is idle. Execution
of the CPU is governed by an internal state machine. A
4-bit control code is clocked in using PGC and PGD,
and this control code is used to command the CPU
(see Table 11-1).
The SIX control code is used to send instructions to the
CPU for execution, while the REGOUT control code is
used to read data out of the device via the VISI register.
The operation details of ICSP mode are provided in
TABLE 11-1:
CPU CONTROL CODES IN
ICSP MODE
4-bit
Control
Code
Mnemonic
Description
0000b
SIX
Shift in 24-bit instruction
and execute.
0001b
REGOUT
Shift out the VISI
register.
0010b-1111b N/A
Reserved.
11.2.1
SIX SERIAL INSTRUCTION
EXECUTION
The SIX control code allows execution of dsPIC30F
assembly instructions. When the SIX code is received,
the CPU is suspended for 24 clock cycles as the
instruction is then clocked into the internal buffer. Once
the instruction is shifted in, the state machine allows it
to be executed over the next four clock cycles. While
the received instruction is executed, the state machine
simultaneously shifts in the next 4-bit command (see
Note 1: During ICSP operation, the operating
frequency of PGC must not exceed
5 MHz.
2: Because ICSP is slower, it is recom-
mended that only Enhanced ICSP (E-
ICSP) mode be used for device program-
ming, as described in Section 5.1
Note 1: Coming out of the ICSP entry sequence,
the first 4-bit control code is always
forced to SIX and a forced NOP instruc-
tion is executed by the CPU. Five addi-
tional PGC clocks are needed on start-
up, thereby resulting in a 9-bit SIX com-
mand instead of the normal 4-bit SIX
command. After the forced SIX is clocked
in, ICSP operation resumes as normal
(the next 24 clock cycles load the first
instruction word to the CPU). See
Figure 11-1 for details.
2: TBLRDH, TBLRDL, TBLWTH and TBLWTL
instructions must be followed by a NOP
instruction.
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相关代理商/技术参数 |
参数描述 |
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| DSPIC30F2012A20E/ML | 制造商:MICROCHIP 制造商全称:Microchip Technology 功能描述:High-Performance, 16-Bit Digital Signal Controllers |
| DSPIC30F2012A-20E/ML | 制造商:MICROCHIP 制造商全称:Microchip Technology 功能描述:High-Performance, 16-Bit Digital Signal Controllers |
| DSPIC30F2012A20E/P | 制造商:MICROCHIP 制造商全称:Microchip Technology 功能描述:High-Performance, 16-Bit Digital Signal Controllers |
| DSPIC30F2012A-20E/P | 制造商:MICROCHIP 制造商全称:Microchip Technology 功能描述:High-Performance, 16-Bit Digital Signal Controllers |
| DSPIC30F2012A20E/SO | 制造商:MICROCHIP 制造商全称:Microchip Technology 功能描述:High-Performance, 16-Bit Digital Signal Controllers |
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