- 您现在的位置：买卖IC网 > PDF目录3856 > DSPIC30F2012-30I/ML (Microchip Technology)IC DSPIC MCU/DSP 12K 28QFN PDF资料下载
参数资料
| 型号： | DSPIC30F2012-30I/ML |
| 厂商： | Microchip Technology |
| 文件页数： | 56/66页 |
| 文件大小： | 0K |
| 描述： | IC DSPIC MCU/DSP 12K 28QFN |
| 产品培训模块： | Serial Communications using dsPIC30F I2C Serial Communications using dsPIC30F SPI Serial Communications using dsPIC30F UART dsPIC30F 12 bit ADC - Part 2 dsPIC30F Addressing Modes - Part 1 dsPIC30F Architecture - Part 1 dsPIC30F DSP Engine & ALU dsPIC30F Interrupts dsPIC30F Motor Control PWM dsPIC Timers Asynchronous Stimulus dsPIC30F Addressing Modes - Part 2 dsPIC30F Architecture - Part 2 dsPIC30F 12-bit ADC Part 1 |
| 标准包装： | 61 |
| 系列： | dsPIC™ 30F |
| 核心处理器： | dsPIC |
| 芯体尺寸： | 16-位 |
| 速度： | 30 MIP |
| 连通性： | I²C，SPI，UART/USART |
| 外围设备： | 欠压检测/复位，POR，PWM，WDT |
| 输入/输出数： | 20 |
| 程序存储器容量： | 12KB（4K x 24） |
| 程序存储器类型： | 闪存 |
| RAM 容量： | 1K x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 2.5 V ~ 5.5 V |
| 数据转换器： | A/D 10x12b |
| 振荡器型： | 内部 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 28-VQFN 裸露焊盘 |
| 包装： | 管件 |
| 产品目录页面： | 650 (CN2011-ZH PDF) |
| 配用： | AC164322-ND - MODULE SOCKET MPLAB PM3 28/44QFN DV164005-ND - KIT ICD2 SIMPLE SUIT W/USB CABLE |
| 其它名称： | DSPIC30F201230IML |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页当前第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页
dsPIC30F Flash Programming Specification
DS70102K-page 6
2010 Microchip Technology Inc.
5.2
Entering Enhanced ICSP Mode
The Enhanced ICSP mode is entered by holding PGC
and PGD high, and then raising MCLR/VPP to VIHH
(high voltage), as illustrated in Figure 5-2. In this mode,
the code memory, data EEPROM and Configuration
bits can be efficiently programmed using the program-
ming executive commands that are serially transferred
using PGC and PGD.
FIGURE 5-2:
ENTERING ENHANCED
ICSP MODE
5.3
Chip Erase
Before a chip can be programmed, it must be erased.
The Bulk Erase command (ERASEB) is used to perform
this task. Executing this command with the MS
command field set to 0x3 erases all code memory, data
EEPROM and code-protect Configuration bits. The
Chip Erase process sets all bits in these three memory
regions to ‘1’.
Since non-code-protect Configuration bits cannot be
erased, they must be manually set to ‘1’ using multiple
PROGC commands. One PROGC command must be
sent for each Configuration register (see Section 5.7
If Advanced Security features are enabled, then indi-
vidual Segment Erase operations would need to be
performed, depending on which segment needs to be
programmed at a given stage of system programming.
The user should have the flexibility to select specific
segments for programming.
Note:
The Device ID registers cannot be erased.
These registers remain intact after a Chip
Erase is performed.
5.4
Blank Check
The term “Blank Check” means to verify that the device
has been successfully erased and has no programmed
memory cells. A blank or erased memory cell reads as
‘1’. The following memories must be blank checked:
All implemented code memory
All implemented data EEPROM
All Configuration bits (for their default value)
The Device ID registers (0xFF0000:0xFF0002) can be
ignored by the Blank Check since this region stores
device information that cannot be erased. Additionally,
all unimplemented memory space should be ignored
from the Blank Check.
The QBLANK command is used for the Blank Check. It
determines if the code memory and data EEPROM are
erased by testing these memory regions. A ‘BLANK’ or
‘NOT BLANK’ response is returned. The READD
command is used to read the Configuration registers. If
it is determined that the device is not blank, it must be
erased (see Section 5.3 “Chip Erase”) before
attempting to program the chip.
Note 1: The sequence that places the device into
Enhanced ICSP mode places all unused
I/Os in the high-impedance state.
2: Before entering Enhanced ICSP mode,
clock switching must be disabled using
ICSP, by programming the FCKSM<1:0>
bits in the FOSC Configuration register to
‘11’ or ‘10’.
3: When in Enhanced ICSP mode, the SPI
output pin (SDO1) will toggle while the
device is being programmed.
MCLR/VPP
P7
PGD
PGD = Input
PGC
VDD
VIHH
P6
相关PDF资料 |
PDF描述 |
|---|---|
| ATMEGA16-16PI | IC AVR MCU 16K 16MHZ IND 40-DIP |
| ATMEGA128-16MI | IC AVR MCU 128K 16MHZ IND 64-QFN |
| T89C51CC02UA-SITIM | IC 8051 MCU FLASH 16K 28PLCC |
| T89C51CC01UA-SLSIM | IC 8051 MCU FLASH 32K 44PLCC |
| T89C51CC01UA-RLTIM | IC 8051 MCU FLASH 32K 44VQFP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| DSPIC30F2012A20E/ML | 制造商:MICROCHIP 制造商全称:Microchip Technology 功能描述:High-Performance, 16-Bit Digital Signal Controllers |
| DSPIC30F2012A-20E/ML | 制造商:MICROCHIP 制造商全称:Microchip Technology 功能描述:High-Performance, 16-Bit Digital Signal Controllers |
| DSPIC30F2012A20E/P | 制造商:MICROCHIP 制造商全称:Microchip Technology 功能描述:High-Performance, 16-Bit Digital Signal Controllers |
| DSPIC30F2012A-20E/P | 制造商:MICROCHIP 制造商全称:Microchip Technology 功能描述:High-Performance, 16-Bit Digital Signal Controllers |
| DSPIC30F2012A20E/SO | 制造商:MICROCHIP 制造商全称:Microchip Technology 功能描述:High-Performance, 16-Bit Digital Signal Controllers |
发布紧急采购，3分钟左右您将得到回复。