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型号： DSPIC30F3012-20I/P
厂商： Microchip Technology
文件页数： 119/161页
文件大小： 0K
描述： IC DSPIC MCU/DSP 24K 18DIP
产品培训模块： Serial Communications using dsPIC30F I2C
Serial Communications using dsPIC30F SPI
Serial Communications using dsPIC30F UART
dsPIC30F 12 bit ADC - Part 2
dsPIC30F Addressing Modes - Part 1
dsPIC30F Architecture - Part 1
dsPIC30F DSP Engine & ALU
dsPIC30F Interrupts
dsPIC30F Motor Control PWM
dsPIC Timers
Asynchronous Stimulus
dsPIC30F Addressing Modes - Part 2
dsPIC30F Architecture - Part 2
dsPIC30F 12-bit ADC Part 1
标准包装： 25
系列： dsPIC™ 30F
核心处理器： dsPIC
芯体尺寸： 16-位
速度： 20 MIPS
连通性： I²C，SPI，UART/USART
外围设备： 欠压检测/复位，POR，PWM，WDT
输入/输出数： 12
程序存储器容量： 24KB（8K x 24）
程序存储器类型： 闪存
EEPROM 大小： 1K x 8
RAM 容量： 2K x 8
电压 - 电源 (Vcc/Vdd)： 2.5 V ~ 5.5 V
数据转换器： A/D 8x12b
振荡器型： 内部
工作温度： -40°C ~ 85°C
封装/外壳： 18-DIP（0.300"，7.62mm）
包装： 管件
配用： AC30F005-ND - MODULE SCKT DSPIC30F 18DIP/SOIC
ACICE0202-ND - ADAPTER MPLABICE 18P 300 MIL
其它名称： DSPIC30F3012-20IP
dsPIC30F2011/2012/3012/3013
DS70139G-page 46
2010 Microchip Technology Inc.
4.2.3
MODULO ADDRESSING
APPLICABILITY
Modulo Addressing can be applied to the Effective
Address (EA) calculation associated with any W
register. It is important to realize that the address
boundaries check for addresses less than, or greater
than the upper (for incrementing buffers), and lower (for
decrementing buffers) boundary addresses (not just
equal to). Address changes may, therefore, jump
beyond boundaries and still be adjusted correctly.
4.3
Bit-Reversed Addressing
Bit-Reversed Addressing is intended to simplify data
re-ordering for radix-2 FFT algorithms. It is supported
by the X AGU for data writes only.
The modifier, which may be a constant value or register
contents, is regarded as having its bit order reversed. The
address source and destination are kept in normal order.
Thus, the only operand requiring reversal is the modifier.
4.3.1
BIT-REVERSED ADDRESSING
IMPLEMENTATION
Bit-Reversed Addressing is enabled when:
BWM (W register selection) in the MODCON reg-
ister is any value other than ‘15’ (the stack cannot
be accessed using Bit-Reversed Addressing)
and
The BREN bit is set in the XBREV register
and
The addressing mode used is Register Indirect
with Pre-Increment or Post-Increment.
If the length of a bit-reversed buffer is M = 2N bytes,
then the last ‘N’ bits of the data buffer Start address
must be zeros.
XB<14:0> is the bit-reversed address modifier or ‘pivot
point’ which is typically a constant. In the case of an
FFT computation, its value is equal to half of the FFT
data buffer size.
When enabled, Bit-Reversed Addressing is only
executed for register indirect with pre-increment or
post-increment addressing and word-sized data writes.
It does not function for any other addressing mode or
for byte-sized data. Normal addresses are generated
instead. When Bit-Reversed Addressing is active, the
W address pointer is always added to the address
modifier (XB) and the offset associated with the
Register Indirect Addressing mode is ignored. In
addition, as word-sized data is a requirement, the LSb
of the EA is ignored (and always clear).
If Bit-Reversed Addressing has already been enabled
by setting the BREN bit (XBREV<15>), then a write to
the XBREV register should not be immediately followed
by an indirect read operation using the W register that
has been designated as the bit-reversed pointer.
Note:
The modulo corrected Effective Address
is written back to the register only when
Pre-Modify or Post-Modify Addressing
mode is used to compute the EA. When
an address offset (e.g., [W7+W2]) is used,
Modulo address correction is performed,
but the contents of the register remain
unchanged.
Note:
All bit-reversed EA calculations assume
word-sized data (LSb of every EA is
always clear). The XB value is scaled
accordingly to generate compatible (byte)
addresses.
Note:
Modulo
Addressing
and
Bit-Reversed
Addressing
should
not
be
enabled
together. In the event that the user
attempts to do this, Bit-Reversed Address-
ing assumes priority when active for the X
WAGU, and X WAGU Modulo Addressing
is disabled. However, Modulo Addressing
continues to function in the X RAGU.
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相关代理商/技术参数
参数描述
DSPIC30F3012-30I/ML 功能描述:数字信号处理器和控制器 - DSP, DSC Sensor RoHS:否 制造商:Microchip Technology 核心:dsPIC 数据总线宽度:16 bit 程序存储器大小:16 KB 数据 RAM 大小:2 KB 最大时钟频率:40 MHz 可编程输入/输出端数量:35 定时器数量:3 设备每秒兆指令数:50 MIPs 工作电源电压:3.3 V 最大工作温度:+ 85 C 封装 / 箱体:TQFP-44 安装风格:SMD/SMT
DSPIC30F3012-30I/P 功能描述:数字信号处理器和控制器 - DSP, DSC Sensor RoHS:否 制造商:Microchip Technology 核心:dsPIC 数据总线宽度:16 bit 程序存储器大小:16 KB 数据 RAM 大小:2 KB 最大时钟频率:40 MHz 可编程输入/输出端数量:35 定时器数量:3 设备每秒兆指令数:50 MIPs 工作电源电压:3.3 V 最大工作温度:+ 85 C 封装 / 箱体:TQFP-44 安装风格:SMD/SMT
DSPIC30F3012-30I/SO 功能描述:数字信号处理器和控制器 - DSP, DSC Sensor RoHS:否 制造商:Microchip Technology 核心:dsPIC 数据总线宽度:16 bit 程序存储器大小:16 KB 数据 RAM 大小:2 KB 最大时钟频率:40 MHz 可编程输入/输出端数量:35 定时器数量:3 设备每秒兆指令数:50 MIPs 工作电源电压:3.3 V 最大工作温度:+ 85 C 封装 / 箱体:TQFP-44 安装风格:SMD/SMT
dsPIC30F3012T-20E/ML 功能描述:数字信号处理器和控制器 - DSP, DSC 44LD 20MIPS 24 KB RoHS:否 制造商:Microchip Technology 核心:dsPIC 数据总线宽度:16 bit 程序存储器大小:16 KB 数据 RAM 大小:2 KB 最大时钟频率:40 MHz 可编程输入/输出端数量:35 定时器数量:3 设备每秒兆指令数:50 MIPs 工作电源电压:3.3 V 最大工作温度:+ 85 C 封装 / 箱体:TQFP-44 安装风格:SMD/SMT
dsPIC30F3012T-20E/SO 功能描述:数字信号处理器和控制器 - DSP, DSC 18LD 20MIPS 24 KB RoHS:否 制造商:Microchip Technology 核心:dsPIC 数据总线宽度:16 bit 程序存储器大小:16 KB 数据 RAM 大小:2 KB 最大时钟频率:40 MHz 可编程输入/输出端数量:35 定时器数量:3 设备每秒兆指令数:50 MIPs 工作电源电压:3.3 V 最大工作温度:+ 85 C 封装 / 箱体:TQFP-44 安装风格:SMD/SMT
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