参数资料
型号: DSPIC30F3014-20I/PT
厂商: Microchip Technology
文件页数: 33/153页
文件大小: 0K
描述: IC DSPIC MCU/DSP 24K 44TQFP
产品培训模块: Serial Communications using dsPIC30F I2C
Serial Communications using dsPIC30F SPI
Serial Communications using dsPIC30F UART
dsPIC30F 12 bit ADC - Part 2
dsPIC30F Addressing Modes - Part 1
dsPIC30F Architecture - Part 1
dsPIC30F DSP Engine & ALU
dsPIC30F Interrupts
dsPIC30F Motor Control PWM
dsPIC Timers
Asynchronous Stimulus
dsPIC30F Addressing Modes - Part 2
dsPIC30F Architecture - Part 2
dsPIC30F 12-bit ADC Part 1
标准包装: 160
系列: dsPIC™ 30F
核心处理器: dsPIC
芯体尺寸: 16-位
速度: 20 MIPS
连通性: I²C,SPI,UART/USART
外围设备: 欠压检测/复位,POR,PWM,WDT
输入/输出数: 30
程序存储器容量: 24KB(8K x 24)
程序存储器类型: 闪存
EEPROM 大小: 1K x 8
RAM 容量: 2K x 8
电压 - 电源 (Vcc/Vdd): 2.5 V ~ 5.5 V
数据转换器: A/D 13x12b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 44-TQFP
包装: 托盘
配用: XLT80PT3-ND - SOCKET TRAN ICE 80MQFP/TQFP
AC164305-ND - MODULE SKT FOR PM3 44TQFP
其它名称: DSPIC30F301420IPT
dsPIC30F3014/4013
DS70138G-page 128
2010 Microchip Technology Inc.
18.3.18
SLOT STATUS BITS
The SLOT<3:0> status bits in the DCISTAT SFR indi-
cate the current active time slot. These bits correspond
to the value of the Frame Sync generator counter. The
user may poll these status bits in software when a DCI
interrupt occurs to determine what time slot data was
last received and which time slot data should be loaded
into the TXBUF registers.
18.3.19
CSDO MODE BIT
The CSDOM control bit controls the behavior of the
CSDO pin during unused transmit slots. A given trans-
mit time slot is unused if it’s corresponding TSEx bit in
the TSCON SFR is cleared.
If the CSDOM bit is cleared (default), the CSDO pin is
low during unused time slot periods. This mode is used
when there are only two devices attached to the serial
bus.
If the CSDOM bit is set, the CSDO pin is tri-stated dur-
ing unused time slot periods. This mode allows multiple
devices to share the same CSDO line in a multichannel
application. Each device on the CSDO line is config-
ured so that it only transmits data during specific time
slots. No two devices transmit data during the same
time slot.
18.3.20
DIGITAL LOOPBACK MODE
Digital Loopback mode is enabled by setting the
DLOOP control bit in the DCICON1 SFR. When the
DLOOP bit is set, the module internally connects the
CSDO signal to CSDI. The actual data input on the
CSDI I/O pin is ignored in Digital Loopback mode.
18.3.21
UNDERFLOW MODE CONTROL BIT
When an underflow occurs, one of two actions may
occur depending on the state of the Underflow mode
(UNFM) control bit in the DCICON1 SFR. If the UNFM
bit is cleared (default), the module transmits ‘0’s on the
CSDO pin during the active time slot for the buffer loca-
tion. In this operating mode, the Codec device attached
to the DCI module is simply fed digital ‘silence’. If the
UNFM control bit is set, the module transmits the last
data written to the buffer location. This operating mode
permits the user to send continuous data to the Codec
device without consuming CPU overhead.
18.4
DCI Module Interrupts
The frequency of DCI module interrupts is dependent
on the BLEN<1:0> control bits in the DCICON2 SFR.
An interrupt to the CPU is generated each time the set
buffer length has been reached and a shadow register
transfer takes place. A shadow register transfer is
defined as the time when the previously written TXBUF
values are transferred to the transmit shadow registers
and new received values in the receive shadow
registers are transferred into the RXBUF registers.
18.5
DCI Module Operation During CPU
Sleep and Idle Modes
18.5.1
DCI MODULE OPERATION DURING
CPU SLEEP MODE
The DCI module has the ability to operate while in
Sleep mode and wake the CPU when the CSCK signal
is supplied by an external device (CSCKD = 1). The
DCI module generates an asynchronous interrupt
when a DCI buffer transfer has completed and the CPU
is in Sleep mode.
18.5.2
DCI MODULE OPERATION DURING
CPU IDLE MODE
If the DCISIDL control bit is cleared (default), the mod-
ule continues to operate normally even in Idle mode. If
the DCISIDL bit is set, the module halts when Idle
mode is asserted.
18.6
AC-Link Mode Operation
The AC-Link protocol is a 256-bit frame with one 16-bit
data slot, followed by twelve 20-bit data slots. The DCI
module has two operating modes for the AC-Link pro-
tocol. These operating modes are selected by the
COFSM<1:0> control bits in the DCICON1 SFR. The
first AC-Link mode is called ‘16-bit AC-Link mode’ and
is selected by setting COFSM<1:0> = 10. The second
AC-Link mode is called ‘20-bit AC-Link mode’ and is
selected by setting COFSM<1:0> = 11.
18.6.1
16-BIT AC-LINK MODE
In the 16-bit AC-Link mode, data word lengths are
restricted to 16 bits. Note that this restriction only
affects the 20-bit data time slots of the AC-Link proto-
col. For received time slots, the incoming data is simply
truncated to 16 bits. For outgoing time slots, the 4 LSbs
of the data word are set to ‘0’ by the module. This trun-
cation of the time slots limits the A/D and DAC data to
16 bits but permits proper data alignment in the TXBUF
and RXBUF registers. Each RXBUF and TXBUF
register contains one data time slot value.
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DSPIC30F3014-30I/P 功能描述:数字信号处理器和控制器 - DSP, DSC General Purpose RoHS:否 制造商:Microchip Technology 核心:dsPIC 数据总线宽度:16 bit 程序存储器大小:16 KB 数据 RAM 大小:2 KB 最大时钟频率:40 MHz 可编程输入/输出端数量:35 定时器数量:3 设备每秒兆指令数:50 MIPs 工作电源电压:3.3 V 最大工作温度:+ 85 C 封装 / 箱体:TQFP-44 安装风格:SMD/SMT
DSPIC30F3014-30I/P 制造商:Microchip Technology Inc 功能描述:16- Bit Digital Signal Controller
DSPIC30F3014-30I/PT 功能描述:数字信号处理器和控制器 - DSP, DSC General Purpose RoHS:否 制造商:Microchip Technology 核心:dsPIC 数据总线宽度:16 bit 程序存储器大小:16 KB 数据 RAM 大小:2 KB 最大时钟频率:40 MHz 可编程输入/输出端数量:35 定时器数量:3 设备每秒兆指令数:50 MIPs 工作电源电压:3.3 V 最大工作温度:+ 85 C 封装 / 箱体:TQFP-44 安装风格:SMD/SMT
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