参数资料
型号: DSPIC30F3014-20I/PT
厂商: Microchip Technology
文件页数: 42/153页
文件大小: 0K
描述: IC DSPIC MCU/DSP 24K 44TQFP
产品培训模块: Serial Communications using dsPIC30F I2C
Serial Communications using dsPIC30F SPI
Serial Communications using dsPIC30F UART
dsPIC30F 12 bit ADC - Part 2
dsPIC30F Addressing Modes - Part 1
dsPIC30F Architecture - Part 1
dsPIC30F DSP Engine & ALU
dsPIC30F Interrupts
dsPIC30F Motor Control PWM
dsPIC Timers
Asynchronous Stimulus
dsPIC30F Addressing Modes - Part 2
dsPIC30F Architecture - Part 2
dsPIC30F 12-bit ADC Part 1
标准包装: 160
系列: dsPIC™ 30F
核心处理器: dsPIC
芯体尺寸: 16-位
速度: 20 MIPS
连通性: I²C,SPI,UART/USART
外围设备: 欠压检测/复位,POR,PWM,WDT
输入/输出数: 30
程序存储器容量: 24KB(8K x 24)
程序存储器类型: 闪存
EEPROM 大小: 1K x 8
RAM 容量: 2K x 8
电压 - 电源 (Vcc/Vdd): 2.5 V ~ 5.5 V
数据转换器: A/D 13x12b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 44-TQFP
包装: 托盘
配用: XLT80PT3-ND - SOCKET TRAN ICE 80MQFP/TQFP
AC164305-ND - MODULE SKT FOR PM3 44TQFP
其它名称: DSPIC30F301420IPT
dsPIC30F3014/4013
DS70138G-page 136
2010 Microchip Technology Inc.
FIGURE 19-3:
CONVERTING 1 CHANNEL AT 200 ksps, AUTO-SAMPLE START, 1 TAD
SAMPLING TIME
19.8
A/D Acquisition Requirements
The analog input model of the 12-bit A/D converter is
shown in Figure 19-4. The total sampling time for the
A/D is a function of the internal amplifier settling time
and the holding capacitor charge time.
For the A/D converter to meet its specified accuracy,
the Charge Holding Capacitor (CHOLD) must be
allowed to fully charge to the voltage level on the
analog input pin. The Source Impedance (RS), the
Interconnect Impedance (RIC) and the Internal Sam-
pling Switch (RSS) Impedance combine to directly
affect the time required to charge the capacitor, CHOLD.
The combined impedance of the analog sources must
therefore be small enough to fully charge the holding
capacitor within the chosen sample time. To minimize
the effects of pin leakage currents on the accuracy of
the A/D converter, the maximum recommended source
impedance, RS, is 2.5 k
. After the analog input chan-
nel is selected (changed), this sampling function must
be completed prior to starting the conversion. The inter-
nal holding capacitor will be in a discharged state prior
to each sample operation.
FIGURE 19-4:
12-BIT A/D CONVERTER ANALOG INPUT MODEL
TCONV
= 14 TAD
TSAMP
= 1 TAD
TSAMP
= 1 TAD
ADCLK
SAMP
DONE
ADCBUF0
ADCBUF1
Instruction Execution BSET ADCON1, ASAM
TCONV
= 14 TAD
CPIN
VA
Rs
ANx
VT = 0.6V
ILEAKAGE
RIC
250
Sampling
Switch
RSS
CHOLD
= DAC capacitance
VSS
VDD
= 18 pF
500 nA
Legend: CPIN
VT
ILEAKAGE
RIC
RSS
CHOLD
= Input Capacitance
= Threshold Voltage
= Leakage Current at the pin due to
= Interconnect Resistance
= Sampling Switch Resistance
= Sample/Hold Capacitance (from DAC)
various junctions
Note: CPIN value depends on device package and is not tested. Effect of CPIN negligible if Rs
2.5 k.
RSS
3 k
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