参数资料
型号: DSPIC30F5016-30I/PT
厂商: Microchip Technology
文件页数: 85/129页
文件大小: 0K
描述: IC DSPIC MCU/DSP 66K 80TQFP
产品培训模块: dsPIC30F Quadrature Encoder Interface
Serial Communications using dsPIC30F CAN
Serial Communications using dsPIC30F I2C
Serial Communications using dsPIC30F SPI
Serial Communications using dsPIC30F UART
dsPIC30F 12 bit ADC - Part 2
dsPIC30F Addressing Modes - Part 1
dsPIC30F Architecture - Part 1
dsPIC30F DSP Engine & ALU
Asynchronous Stimulus
dsPIC30F Addressing Modes - Part 2
dsPIC30F Architecture - Part 2
dsPIC30F 12-bit ADC Part 1
标准包装: 119
系列: dsPIC™ 30F
核心处理器: dsPIC
芯体尺寸: 16-位
速度: 30 MIP
连通性: CAN,I²C,SPI,UART/USART
外围设备: 高级欠压探测/复位,电机控制 PWM,QEI,POR,PWM,WDT
输入/输出数: 68
程序存储器容量: 66KB(22K x 24)
程序存储器类型: 闪存
EEPROM 大小: 1K x 8
RAM 容量: 2K x 8
电压 - 电源 (Vcc/Vdd): 2.5 V ~ 5.5 V
数据转换器: A/D 16x10b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 80-TQFP
包装: 托盘
产品目录页面: 651 (CN2011-ZH PDF)
配用: AC164320-ND - MODULE SKT MPLAB PM3 80TQFP
AC30F007-ND - MODULE SKT FOR DSPIC30F 80TQFP
DV164005-ND - KIT ICD2 SIMPLE SUIT W/USB CABLE
其它名称: DSPIC30F501630IPT
2008 Microchip Technology Inc.
DS70149D-page 59
dsPIC30F5015/5016
7.3
Writing to the Data EEPROM
To write an EEPROM data location, the following
sequence must be followed:
1.
Erase data EEPROM word.
a) Select word, data EEPROM, erase and set
WREN bit in NVMCON register.
b) Write address of word to be erased into
NVMADRU/NVMADR.
c)
Enable NVM interrupt (optional).
d) Write ‘0x55’ to NVMKEY.
e) Write ‘0xAA’ to NVMKEY.
f)
Set the WR bit. This will begin erase cycle.
g) Either poll NVMIF bit or wait for NVMIF
interrupt.
h) The WR bit is cleared when the erase cycle
ends.
2.
Write data word into data EEPROM write
latches.
3.
Program 1 data word into data EEPROM.
a) Select word, data EEPROM, program and
set WREN bit in NVMCON register.
b) Enable NVM write done interrupt (optional).
c)
Write ‘0x55’ to NVMKEY.
d) Write ‘0xAA’ to NVMKEY.
e) Set the WR bit. This will begin program
cycle.
f)
Either poll NVMIF bit or wait for NVM
interrupt.
g) The WR bit is cleared when the write cycle
ends.
The write will not initiate if the above sequence is not
exactly followed (write 0x55 to NVMKEY, write 0xAA to
NVMCON, then set WR bit) for each word. It is strongly
recommended that interrupts be disabled during this
code segment.
Additionally, the WREN bit in NVMCON must be set to
enable writes. This mechanism prevents accidental
writes to data EEPROM, due to unexpected code
execution. The WREN bit should be kept clear at all
times, except when updating the EEPROM. The
WREN bit is not cleared by hardware.
After a write sequence has been initiated, clearing the
WREN bit will not affect the current write cycle. The WR
bit will be inhibited from being set unless the WREN bit
is set. The WREN bit must be set on a previous
instruction. Both WR and WREN cannot be set with the
same instruction.
At the completion of the write cycle, the WR bit is
cleared in hardware and the Nonvolatile Memory Write
Complete Interrupt Flag bit (NVMIF) is set. The user
may either enable this interrupt, or poll this bit. NVMIF
must be cleared by software.
7.3.1
WRITING A WORD OF DATA
EEPROM
Once the user has erased the word to be programmed,
then a table write instruction is used to write one write
latch, as shown in Example 7-4.
EXAMPLE 7-4:
DATA EEPROM WORD WRITE
; Point to data memory
MOV
#LOW_ADDR_WORD,W0
; Init pointer
MOV
#HIGH_ADDR_WORD,W1
MOV
W1,TBLPAG
MOV
#LOW(WORD),W2
; Get data
TBLWTL
W2,[ W0]
; Write data
; The NVMADR captures last table access address
; Select data EEPROM for 1 word op
MOV
#0x4004,W0
MOV
W0,NVMCON
; Operate key to allow write operation
DISI
#5
; Block all interrupts with priority <7
; for next 5 instructions
MOV
#0x55,W0
MOV
W0,NVMKEY
; Write the 0x55 key
MOV
#0xAA,W1
MOV
W1,NVMKEY
; Write the 0xAA key
BSET
NVMCON,#WR
; Initiate program sequence
NOP
; Write cycle will complete in 2mS. CPU is not stalled for the Data Write Cycle
; User can poll WR bit, use NVMIF or Timer IRQ to determine write complete
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