参数资料
型号: EDI816256CA
英文描述: 256Kx16 Monolithic SRAM(CMOS,256Kx16单片静态RAM)
中文描述: 256Kx16单片的SRAM(的CMOS,256Kx16单片静态内存)
文件页数: 3/7页
文件大小: 118K
代理商: EDI816256CA
3
White Electronic Designs Corporation Phoenix, AZ (602) 437-1520
EDI816256CA
AC CHARACTERISTICS – READ CYCLE
(VCC = 5.0V, VSS = 0V, TA = -55
°C to +125°C)
Symbol
17ns
20ns
25ns
35ns
Parameter
JEDEC
Alt.
Min
Max
Min
Max
Min
Max
Min
Max
Units
Read Cycle Time
tAVAV
tRC
17
20
25
35
ns
Address Access Time
tAVQV
tAA
17
20
25
35
ns
Chip Enable Access Time
tELQV
tACS
17
20
25
35
ns
Chip Enable to Output in Low Z (1)
tELQX
tCLZ
25
5
ns
Chip Disable to Output in High Z (1)
tEHQZ
tCHZ
07
0
8
0
10
ns
Output Hold from Address Change
tAVQX
tOH
00
0
ns
Output Enable to Output Valid
tGLQV
tOE
10
12
15
ns
Output Enable to Output in Low Z (1)
tGLQX
tOLZ
00
0
ns
Output Disable to Output in High Z(1)
tGHQZ
tOHZ
07
0
8
0
10
ns
LB, UB Access Time
tUBLQV
tBA
10
12
15
ns
tLBLQV
LB, UB Enable to Low Z Output
tUBLQX
tBLZ
00
0
ns
tLBLQX
LB, UB Disable to High Z Output
tUBHQZ
tBHZ
07
0
8
0
10
ns
tLBHQZ
NOTE:
1. This parameter is guaranteed by design but not tested.
AC CHARACTERISTICS – WRITE CYCLE
(VCC = 5.0V, VSS = 0V, TA = -55
°C to +125°C)
Symbol
17ns
20ns
25ns
35ns
Parameter
JEDEC
Alt.
Min
Max
Min
Max
Min
Max
Min
Max
Units
Write Cycle Time
tAVAV
tWC
17
20
25
35
ns
Chip Enable to End of Write
tELWH
tCW
14
15
17
20
ns
tELEH
tCW
14
15
17
20
ns
Address Setup Time
tAVWL
tAS
00
0
ns
tAVEL
tAS
00
0
ns
tAVUBL
tAS
00
0
ns
Address Valid to End of Write
tAVWH
tAW
14
15
17
20
ns
tAVEH
tAW
14
15
17
20
ns
tAVUBH
tAW
14
15
17
20
ns
Write Pulse Width
tWLWH
tWP
14
15
17
ns
tWLEH
tWP
14
15
17
ns
Write Recovery Time
tWHAX
tWR
00
0
ns
tEHAX
tWR
00
0
ns
Data Hold Time
tWHDX
tDH
00
0
ns
tEHDX
tDH
00
0
ns
Write to Output in High Z (1)
tWLQZ
tWHZ
08
0
8
0
10
ns
Data to Write Time
tDVWH
tDW
10
12
15
ns
tDVEH
tDW
10
12
15
ns
Output Active from End of Write (1)
tWHQX
tWLZ
00
0
ns
LB, UB Valid to End of Write
tLBLLBH
tBW
14
16
18
20
ns
tUBLUBH
NOTE:
1. This parameter is guaranteed by design but not tested.
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