参数资料
型号: EFM32G222F128
厂商: Energy Micro
文件页数: 12/136页
文件大小: 0K
描述: IC MCU 32BIT 128KB FLASH 48LQFP
特色产品: EFM32 Gecko
标准包装: 1
系列: Gecko
核心处理器: ARM? Cortex?-M3
芯体尺寸: 32-位
速度: 32MHz
连通性: I²C,IrDA,智能卡,SPI,UART/USART
外围设备: 欠压检测/复位,DMA,POR,PWM,WDT
输入/输出数: 37
程序存储器容量: 128KB(128K x 8)
程序存储器类型: 闪存
RAM 容量: 16K x 8
电压 - 电源 (Vcc/Vdd): 1.8 V ~ 3.8 V
数据转换器: A/D 4x12b,D/A 1x12b
振荡器型: 外部
工作温度: -40°C ~ 85°C
封装/外壳: 48-TQFP
包装: 标准包装
其它名称: 914-1027-6
...the world's most energy friendly microcontrollers
2011-02-04 - d0002_Rev1.00
109
www.energymicro.com
Bits
Name
Function
When this bit is set to 1, the PC value stacked for the exception return points to the instruction
that tried to perform the illegal load of the PC.
[1]
INVSTATE
Invalid state usage fault:
0 = no invalid state usage fault
1 = the processor has attempted to execute an instruction that makes illegal use of the EPSR.
When this bit is set to 1, the PC value stacked for the exception return points to the instruction
that attempted the illegal use of the EPSR.
This bit is not set to 1 if an undefined instruction uses the EPSR.
[0]
UNDEFINSTR
Undefined instruction usage fault:
0 = no undefined instruction usage fault
1 = the processor has attempted to execute an undefined instruction.
When this bit is set to 1, the PC value stacked for the exception return points to the undefined
instruction.
An undefined instruction is an instruction that the processor cannot decode.
Note
The UFSR bits are sticky. This means as one or more fault occurs, the associated bits are
set to 1. A bit that is set to 1 is cleared to 0 only by writing 1 to that bit, or by a reset.
4.3.12 Hard Fault Status Register
The HFSR gives information about events that activate the hard fault handler. See the register summary
in Table 4.12 (p. 94) for its attributes.
This register is read, write to clear. This means that bits in the register read normally, but writing 1 to
any bit clears that bit to 0. The bit assignments are:
31 30
2 1 0
Reserved
29
DEBUGEVT
FORCED
VECTTBL
Reserved
Table 4.29. HFSR bit assignments
Bits
Name
Function
[31]
DEBUGEVT
Reserved for Debug use. When writing to the register you must write 0 to this bit, otherwise
behavior is Unpredictable.
[30]
FORCED
Indicates a forced hard fault, generated by escalation of a fault with configurable priority that
cannot be handles, either because of priority or because it is disabled:
0 = no forced hard fault
1 = forced hard fault.
When this bit is set to 1, the hard fault handler must read the other fault status registers to find
the cause of the fault.
[29:2]
-
Reserved.
[1]
VECTTBL
Indicates a bus fault on a vector table read during exception processing:
0 = no bus fault on vector table read
1 = bus fault on vector table read.
This error is always handled by the hard fault handler.
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