参数资料
型号: EFM32G222F128
厂商: Energy Micro
文件页数: 97/136页
文件大小: 0K
描述: IC MCU 32BIT 128KB FLASH 48LQFP
特色产品: EFM32 Gecko
标准包装: 1
系列: Gecko
核心处理器: ARM? Cortex?-M3
芯体尺寸: 32-位
速度: 32MHz
连通性: I²C,IrDA,智能卡,SPI,UART/USART
外围设备: 欠压检测/复位,DMA,POR,PWM,WDT
输入/输出数: 37
程序存储器容量: 128KB(128K x 8)
程序存储器类型: 闪存
RAM 容量: 16K x 8
电压 - 电源 (Vcc/Vdd): 1.8 V ~ 3.8 V
数据转换器: A/D 4x12b,D/A 1x12b
振荡器型: 外部
工作温度: -40°C ~ 85°C
封装/外壳: 48-TQFP
包装: 标准包装
其它名称: 914-1027-6
...the world's most energy friendly microcontrollers
2011-02-04 - d0002_Rev1.00
63
www.energymicro.com
where:
S
is an optional suffix. If S is specified, the condition code flags are updated on the result of
the operation, see Section 3.3.7 (p. 43) .
cond
is an optional condition code, see Section 3.3.7 (p. 43) .
Rd
is the destination register.
Operand2
is a flexible second operand. See Section 3.3.3 (p. 38) for details of the options.
imm16
is any value in the range 0-65535.
3.5.6.2 Operation
The MOV instruction copies the value of Operand2 into Rd.
When Operand2 in a MOV instruction is a register with a shift other than LSL #0, the preferred syntax
is the corresponding shift instruction:
ASR{S}{cond} Rd, Rm, #n is the preferred syntax for MOV{S}{cond} Rd, Rm, ASR #n
LSL{S}{cond} Rd, Rm, #n is the preferred syntax for MOV{S}{cond} Rd, Rm, LSL #n if n != 0
LSR{S}{cond} Rd, Rm, #n is the preferred syntax for MOV{S}{cond} Rd, Rm, LSR #n
ROR{S}{cond} Rd, Rm, #n is the preferred syntax for MOV{S}{cond} Rd, Rm, ROR #n
RRX{S}{cond} Rd, Rm is the preferred syntax for MOV{S}{cond} Rd, Rm, RRX.
Also, the MOV instruction permits additional forms of Operand2 as synonyms for shift instructions:
MOV{S}{cond} Rd, Rm, ASR Rs is a synonym for ASR{S}{cond} Rd, Rm, Rs
MOV{S}{cond} Rd, Rm, LSL Rs is a synonym for LSL{S}{cond} Rd, Rm, Rs
MOV{S}{cond} Rd, Rm, LSR Rs is a synonym for LSR{S}{cond} Rd, Rm, Rs
MOV{S}{cond} Rd, Rm, ROR Rs is a synonym for ROR{S}{cond} Rd, Rm, Rs
The MVN instruction takes the value of Operand2, performs a bitwise logical NOT operation on the value,
and places the result into Rd.
Note
The MOVW instruction provides the same function as MOV, but is restricted to using the
imm16
operand.
3.5.6.3 Restrictions
You can use SP and PC only in the MOV instruction, with the following restrictions:
the second operand must be a register without shift
you must not specify the S suffix.
When Rd is PC in a MOV instruction:
bit[0] of the value written to the PC is ignored
a branch occurs to the address created by forcing bit[0] of that value to 0.
Note
Though it is possible to use MOV as a branch instruction, ARM strongly recommends the
use of a BX or BLX instruction to branch for software portability to the ARM instruction set.
3.5.6.4 Condition flags
If S is specified, these instructions:
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