参数资料
型号: EL7564CMZ-T13
厂商: Intersil
文件页数: 11/17页
文件大小: 0K
描述: IC REG BUCK SYNC ADJ 4A 20SOIC
标准包装: 1,000
类型: 降压(降压)
输出类型: 可调式
输出数: 1
输出电压: 1 V ~ 3.8 V
输入电压: 4.5 V ~ 5.5 V
PWM 型: 电流模式
频率 - 开关: 1MHz
电流 - 输出: 4A
同步整流器:
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 20-SOIC(0.295",7.50mm 宽)
包装: 带卷 (TR)
供应商设备封装: 20-SO
EL7564
T J = 75 + 1.2 – VTJ
NMOS Power FETs and Drive Circuitry
The EL7564 integrates low on-resistance (30m ? ) NMOS
FETs to achieve high efficiency at 4A. In order to use an
NMOS switch for the high-side drive it is necessary to drive
the gate voltage above the source voltage (L X ). This is
accomplished by bootstrapping the V HI pin above the L X
voltage with an external capacitor C VHI and internal switch
and diode. When the low-side switch is turned on and the
L X voltage is close to GND potential, capacitor C VHI is
charged through an internal switch to V DRV , typically 5V. At
the beginning of the next cycle the high-side switch turns
on and the L X pins begin to rise from GND to V IN potential.
As the L X pin rises the positive plate of capacitor C VHI
follows and eventually reaches a value of V DRV + V IN ,
typically 10V, for V DRV = V IN = 5V. This voltage is then
level shifted and used to drive the gate of the high-side
FET, via the V HI pin. A value of 0.22μF for C VHI is
recommended.
Reference
A 1.5% temperature compensated bandgap reference is
integrated in the EL7564. The external V REF capacitor acts
as the dominant pole of the amplifier and can be increased
in size to maximize transient noise rejection. A value of
0.1μF is recommended.
Oscillator
The system clock is generated by an internal relaxation
oscillator with a maximum duty-cycle of approximately 95%.
Operating frequency can be adjusted through C OSC .
When external synchronization is required, always choose
C OSC such that the free-running frequency is at least 20%
lower than that of the sync source to accommodate
component and temperature variations. Figure 21 shows a
typical connection.
Junction Temperature Sensor
An internal temperature sensor continuously monitors die
temperature. In the event that the die temperature exceeds
the thermal trip-point, the system is in a fault state and will
be shut down. The upper and low trip-points are set to 135°C
and 115°C respectively.
The V TJ pin is an accurate indication of the internal silicon
junction temperature (see performance curve.) The junction
temperature T J (°C) can be determined from the following
relation:
-------------------------
0.00384
Where V TJ is the voltage at the V TJ pin in volts.
Power Good and Power On Reset
During power up the output regulator will be disabled until
V IN reaches a value of approximately 4V. About 500mV
hysteresis is present to eliminate noise-induced oscillations.
Under-voltage and over-voltage conditions on the regulator
output are detected through an internal window comparator.
A logic high on the PG output indicates that the regulated
output voltage is within about +10% of the nominal selected
1
20
100pF
BAT54S
2
19
EXTERNAL
OSCILLATOR
390pF
3
5
18
16
6
7
8
9
10
EL7564
15
14
13
12
11
FIGURE 23. OSCILLATOR SYNCHRONIZATION
11
FN7297.3
May 9, 2005
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