参数资料
型号: EL7564CMZ-T13
厂商: Intersil
文件页数: 5/17页
文件大小: 0K
描述: IC REG BUCK SYNC ADJ 4A 20SOIC
标准包装: 1,000
类型: 降压(降压)
输出类型: 可调式
输出数: 1
输出电压: 1 V ~ 3.8 V
输入电压: 4.5 V ~ 5.5 V
PWM 型: 电流模式
频率 - 开关: 1MHz
电流 - 输出: 4A
同步整流器:
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 20-SOIC(0.295",7.50mm 宽)
包装: 带卷 (TR)
供应商设备封装: 20-SO
EL7564
Pin Descriptions
20-PIN SO
28-PIN
(0.300”)
1
2
3
4
5
6, 7
HTSSOP
1
2
3
4
5
6, 7, 8, 9
PIN NAME
VREF
SGND
COSC
VDD
VTJ
PGND
PIN FUNCTION
Bandgap reference bypass capacitor; typically 0.1μF to SGND
Control circuit negative supply or signal ground
Oscillator timing capacitor (see performance curves)
Control circuit positive supply; normally connected to VIN through an RC filter
Junction temperature monitor; connected with 2.2nF to 3.3nF to SGND
Ground return of the regulator; connected to the source of the low-side synchronous NMOS
power FET
8
9
10, 11
13
VIN
STP
Power supply input of the regulator; connected to the drain of the high-side NMOS power FET
Auxiliary supply tracking positive input; tied to regulator output to synchronize start up with a
second supply; leave open for stand alone operation; 2μA internal pull down current
10
14
STN
Auxiliary supply tracking negative input; connect to output of a second supply to synchronize
start up; leave open for stand alone operation; 2μA internal pull up current
11, 12, 13
15, 16
PGND
Ground return of the regulator; connected to the source of the low-side synchronous NMOS
power FET
14, 15
16
18, 19, 20, 21,
22, 23
24
LX
VHI
Inductor drive pin; high current output whose average voltage equals the regulator output
voltage
Positive supply of high-side driver; boot strapped from VDRV to LX with an external 0.22μF
capacitor
17
18
25
26
VDRV
PG
Positive supply of low-side driver and input voltage for high side boot strap
Power good window comparator output; logic 1 when regulator output is within ±10% of target
output voltage
19
27
FB
Voltage feedback input; connected to external resistor divider between VOUT and SGND; a
125nA pull-up current forces VOUT to SGND in the event that FB is floating
20
28
EN
Chip enable, active high; a 2μA internal pull up current enables the device if the pin is left open;
a capacitor can be added at this pin to delay the start of converter
Typical Performance Curves
100
95
90
V IN =5V
V O =3.3V
100
95
90
V IN =5V
V O =3.3V
85
80
75
V O =2.8V
V O =1.8V
85
80
75
V O =2.5V
V O =1.8V
70
65
70
65
60
0
0.5
1
1.5
2
2.5
3
3.5
4
60
0.1
0.6
1.1
1.6
2.1
2.6
3.1
3.6
4.1
LOAD CURRENT I O (A)
FIGURE 1. EL7564CM EFFICIENCY
5
I O (A)
FIGURE 2. EL7564CRE EFFICIENCY
FN7297.3
May 9, 2005
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