参数资料
型号: EM260-RTR
厂商: Silicon Laboratories Inc
文件页数: 5/50页
文件大小: 0K
描述: IC ZIGBEE SYSTEM-ON-CHIP 40-QFN
标准包装: 1
频率: 2.4GHz
数据传输率 - 最大: 250kbps
调制或协议: 802.15.4
应用: ZigBee?
功率 - 输出: -32dBm ~ 3dBm
灵敏度: -97dBm
电源电压: 2.1 V ~ 3.6 V
电流 - 接收: 30mA
电流 - 传输: 34mA
数据接口: PCB,表面贴装
天线连接器: PCB,表面贴装
工作温度: -40°C ~ 85°C
封装/外壳: 40-VFQFN 裸露焊盘
包装: 标准包装
配用: 636-1009-ND - PROGRAMMER USB FLASH EM250/260
其它名称: 636-1007-6
EM260
Table 1. Pin Descriptions
Pin #
Signal
Directio
Description
n
1
2
3
4
5
6
7
8
9
10
VDD_VCO
RF_P
RF_N
VDD_RF
RF_TX_ALT_P
RF_TX_ALT_N
VDD_IF
BIAS_R
VDD_PADSA
TX_ACTIVE
Power
I/O
I/O
Power
O
O
Power
I
Power
O
1.8V VCO supply; should be connected to VREG_OUT
Differential (with RF_N) receiver input/transmitter output
Differential (with RF_P) receiver input/transmitter output
1.8V RF supply (LNA and PA); should be connected to VREG_OUT
Differential (with RF_TX_ALT_N) transmitter output (optional)
Differential (with RF_TX_ALT_P) transmitter output (optional)
1.8V IF supply (mixers and filters); should be connected to VREG_OUT
Bias setting resistor
Analog pad supply (1.8V); should be connected to VREG_OUT
Logic-level control for external RX/TX switch
The EM260 baseband controls TX_ACTIVE and drives it high (1.8V) when in TX mode.
(Refer to Table 6 and section 4.2.2.)
11
12
13
14
15
nRESET
VREG_OUT
VDD_PADS
VDD_CORE
nSSEL_INT
I
Power
Power
Power
I
Active low chip reset (internal pull-up)
Regulator output (1.8V)
Pads supply (2.1 – 3.6V)
1.8V digital core supply; should be connected to VREG_OUT
SPI Slave Select Interrupt (from Host to EM260)
When using the SPI interface, this signal must be connected to nSSEL (Pin 21)
nCTS
I
UART Clear To Send (enables EM260 transmission)
When using the UART interface, this signal should be left unconnected if not used.
16
N.C.
nRTS
I
O
When using the SPI interface, this signal is left not connected.
UART Request To Send (enables Host transmission)
When using the UART interface, this signal should be left unconnected if not used.
17
18
19
20
21
22
23
MOSI
N.C.
MISO
N.C.
VDD_PADS
SCLK
N.C.
nSSEL
N.C.
PTI_EN
PTI_DATA
I
I
O
I
Power
I
I
I
I
O
O
SPI Data, Master Out / Slave In (from Host to EM260)
When using the UART interface, this signal is left not connected.
SPI Data, Master In / Slave Out (from EM260 to Host)
When using the UART interface, this signal is left not connected.
Pads supply (2.1 – 3.6V)
SPI Clock (from Host to EM260)
When using the UART interface, this signal is left not connected.
SPI Slave Select (from Host to EM260)
When using the UART interface, this signal is left not connected.
Frame signal of Packet Trace Interface (PTI)
Data signal of Packet Trace Interface (PTI)
Page 5
120-0260-000M Rev 1.1
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