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| 型号： | EP1C6T240I6ES |
| 厂商： | Altera Corporation |
| 英文描述： | Cyclone FPGA Family Data Sheet |
| 中文描述： | 气旋的FPGA系列数据手册 |
| 文件页数： | 16/104页 |
| 文件大小： | 763K |
| 代理商： | EP1C6T240I6ES |
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2–10
Preliminary
Altera Corporation
January 2007
Cyclone Device Handbook, Volume 1
Figure 2–7. LE in Dynamic Arithmetic Mode
Note to
Figure 2–7
:
(1)
The
addnsub
signal is tied to the carry input for the first LE of a carry chain only.
Carry-Select Chain
The carry-select chain provides a very fast carry-select function between
LEs in dynamic arithmetic mode. The carry-select chain uses the
redundant carry calculation to increase the speed of carry functions. The
LE is configured to calculate outputs for a possible carry-in of 0 and carry-
in of 1 in parallel. The
carry-in0
and
carry-in1
signals from a lower-
order bit feed forward into the higher-order bit via the parallel carry chain
and feed into both the LUT and the next portion of the carry chain. Carry-
select chains can begin in any LE within an LAB.
The speed advantage of the carry-select chain is in the parallel pre-
computation of carry chains. Since the LAB carry-in selects the
precomputed carry chain, not every LE is in the critical path. Only the
propagation delays between LAB carry-in generation (LE 5 and LE 10) are
now part of the critical path. This feature allows the Cyclone architecture
to implement high-speed counters, adders, multipliers, parity functions,
and comparators of arbitrary width.
data1
data2
data3
LUT
addnsub
(LAB Wide)
clock (LAB Wide)
ena (LAB Wide)
aclr (LAB Wide)
ALD/PRE
ADATA
CLRN
D
Q
ENA
Re
g
ister chain
connection
LUT
LUT
LUT
Carry-Out1
Carry-Out0
LAB Carry-In
Carry-In0
Carry-In1
(1)
sclear
(LAB Wide)
sload
(LAB Wide)
LUT chain
connection
Re
g
ister
chain output
Row, column, and
direct link routin
g
Row, column, and
direct link routin
g
Local routin
g
aload
(LAB Wide)
Reg
i
ster
F
eedbac
k
相关PDF资料 |
PDF描述 |
|---|---|
| EP1C6T240I7ES | Cyclone FPGA Family Data Sheet |
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