参数资料
型号: EP1C6T240I6ES
厂商: Altera Corporation
英文描述: Cyclone FPGA Family Data Sheet
中文描述: 气旋的FPGA系列数据手册
文件页数: 40/104页
文件大小: 763K
代理商: EP1C6T240I6ES
2–34
Preliminary
Altera Corporation
January 2007
Cyclone Device Handbook, Volume 1
Figure 2–26
shows the PLL global clock connections.
Figure 2–26. Cyclone PLL Global Clock Connections
Notes to
Figure 2–26
:
(1)
PLL 1 supports one single-ended or LVDS input via pins
CLK0
and
CLK1
.
(2)
PLL2 supports one single-ended or LVDS input via pins
CLK2
and
CLK3
.
(3)
PLL1_OUT
and
PLL2_OUT
support single-ended or LVDS output. If external output is not required, these pins are
available as regular user I/O pins.
(4)
The EP1C3 device in the 100-pin TQFP package does not support external clock output. The EP1C6 device in the
144-pin TQFP package does not support external clock output from PLL2.
Table 2–7
shows the global clock network sources available in Cyclone
devices.
CLK0
CLK1
(1)
PLL1
PLL2
g0
g1
e
g0
g1
e
PLL1_OUT
(3), (4)
CLK2
CLK3
(2)
PLL2_OUT
(3), (4)
G0
G2
G1
G3
G4
G6
G5
G7
Table 2–7. Global Clock Network Sources (Part 1 of 2)
Source
GCLK0
GCLK1
v
GCLK2
v
GCLK3
GCLK4
GCLK5
GCLK6
GCLK7
PLL Counter
Output
PLL1 G0
PLL1 G1
v
v
PLL2 G0
(1)
v
v
PLL2 G1
(1)
v
v
Dedicated
Clock Input
Pins
CLK0
v
v
CLK1
(2)
v
v
CLK2
v
v
CLK3
(2)
v
v
相关PDF资料
PDF描述
EP1C6T240I7ES Cyclone FPGA Family Data Sheet
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EP1C6T256C7ES Cyclone FPGA Family Data Sheet
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