参数资料
型号: EP1C6T240I8ES
厂商: Altera Corporation
英文描述: Cyclone FPGA Family Data Sheet
中文描述: 气旋的FPGA系列数据手册
文件页数: 23/104页
文件大小: 763K
代理商: EP1C6T240I8ES
Altera Corporation
January 2007
2–17
Preliminary
MultiTrack Interconnect
All embedded blocks communicate with the logic array similar to LAB-
to-LAB interfaces. Each block (i.e., M4K memory or PLL) connects to row
and column interconnects and has local interconnect regions driven by
row and column interconnects. These blocks also have direct link
interconnects for fast connections to and from a neighboring LAB.
Table 2–2
shows the Cyclone device's routing scheme.
Table 2–2. Cyclone Device Routing Scheme
Source
Destination
L
R
L
D
R
C
L
v
v
v
M
P
C
R
LUT Chain
Register Chain
Local Interconnect
v
v
v
v
Direct Link
Interconnect
v
v
v
v
v
R4 Interconnect
v
v
v
v
v
v
v
v
v
v
v
v
C4 Interconnect
LE
v
v
v
v
v
M4K RAM Block
PLL
Column IOE
Row IOE
v
v
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