参数资料
型号: EP1C6T240I8ES
厂商: Altera Corporation
英文描述: Cyclone FPGA Family Data Sheet
中文描述: 气旋的FPGA系列数据手册
文件页数: 92/104页
文件大小: 763K
代理商: EP1C6T240I8ES
4–22
Preliminary
Altera Corporation
January 2007
Cyclone Device Handbook, Volume 1
SSTL-2 class II
278
261
320
301
362
340
ps
LVDS
ps
Table 4–41. Cyclone I/O Standard Row Pin Input Delay Adders
I/O Standard
-6 Speed Grade
-7 Speed Grade
-8 Speed Grade
Unit
Min
Max
Min
Max
Min
Max
LVCMOS
0
0
0
ps
3.3-V LVTTL
0
0
0
ps
2.5-V LVTTL
27
31
35
ps
1.8-V LVTTL
182
209
236
ps
1.5-V LVTTL
278
319
361
ps
3.3-V PCI
(1)
0
0
0
ps
SSTL-3 class I
250
250
278
278
261
288
288
320
320
301
325
325
362
362
340
ps
SSTL-3 class II
ps
SSTL-2 class I
ps
SSTL-2 class II
ps
LVDS
ps
Table 4–42. Cyclone I/O Standard Output Delay Adders for Fast Slew Rate on Column Pins (Part 1 of 2)
Standard
-6 Speed Grade
-7 Speed Grade
-8 Speed Grade
Unit
Min
Max
Min
Max
Min
Max
LVCMOS
2 mA
0
0
0
ps
4 mA
489
855
993
563
984
1,142
636
1,112
1,291
ps
8 mA
ps
12 mA
ps
3.3-V LVTTL
4 mA
0
0
0
ps
8 mA
347
858
819
993
400
987
942
1,142
452
1,116
1,065
1,291
ps
12 mA
ps
16 mA
ps
24 mA
ps
Table 4–40. Cyclone I/O Standard Column Pin Input Delay Adders (Part 2 of 2)
I/O Standard
-6 Speed Grade
-7 Speed Grade
-8 Speed Grade
Unit
Min
Max
Min
Max
Min
Max
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