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参数资料
型号： EP20K1000EFC1020-3
元件分类： 数字电位计
英文描述： Quad Digital Controlled Potentiometers (XDCP™); Low Noise, Low Power, I2C® Bus, 256 Taps; Temperature Range: -40°C to 85°C; Package: 10-MSOP
中文描述： FPGA的
文件页数： 63/114页
文件大小： 1623K
代理商： EP20K1000EFC1020-3
52
Altera Corporation
APEX 20K Programmable Logic Device Family Data Sheet
Table 16 summarizes the APEX 20K ClockLock and ClockBoost
parameters for -2 speed grade devices.
Notes:
(1)
To implement the ClockLock and ClockBoost circuitry with the Quartus II
software, designers must specify the input frequency. The Quartus II software
tunes the PLL in the ClockLock and ClockBoost circuitry to this frequency. The
fCLKDEV parameter specifies how much the incoming clock can differ from the
specified frequency during device operation. Simulation does not reflect this
parameter.
(2)
Twenty-five thousand parts per million (PPM) equates to 2.5% of input clock
period.
(3)
During device configuration, the ClockLock and ClockBoost circuitry is configured
before the rest of the device. If the incoming clock is supplied during configuration,
the ClockLock and ClockBoost circuitry locks during configuration because the
tLOCK value is less than the time required for configuration.
(4)
The tJITTER specification is measured under long-term observation.
Table 16. APEX 20K ClockLock & ClockBoost Parameters for -2 Speed Grade
Devices
Symbol
Parameter
Min
Max
Unit
fOUT
Output frequency
25
170
MHz
fCLK1
Input clock frequency (ClockBoost
clock multiplication factor equals 1)
25
170
MHz
fCLK2
Input clock frequency (ClockBoost
clock multiplication factor equals 2)
16
80
MHz
fCLK4
Input clock frequency (ClockBoost
clock multiplication factor equals 4)
10
34
MHz
tOUTDUTY
Duty cycle for ClockLock/ClockBoost-
generated clock
40
60
%
fCLKDEV
Input deviation from user specification
in the Quartus II software (ClockBoost
clock multiplication factor equals one)
(1)
25,000
(2)
PPM
tR
Input rise time
5ns
tF
Input fall time
5ns
tLOCK
Time required for ClockLock/
ClockBoost to acquire lock
(3)
10
s
tSKEW
Skew delay between related
ClockLock/ ClockBoost-generated
clock
500
ps
tJITTER
Jitter on ClockLock/ ClockBoost-
generated clock (4)
200
ps
tINCLKSTB
Input clock stability (measured between
adjacent clocks)
50
ps
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相关代理商/技术参数
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EP20K1000EFC1020-3ES 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA
EP20K1000EFC33-1 功能描述:FPGA - 现场可编程门阵列 CPLD - APEX 20K 2560 Macros 1.8 V RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
EP20K1000EFC33-1X 功能描述:FPGA - 现场可编程门阵列 CPLD - APEX 20K 2560 Macros 1.8 V RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
EP20K1000EFC33-2 功能描述:FPGA - 现场可编程门阵列 CPLD - APEX 20K 2560 Macros 1.8 V RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
EP20K1000EFC33-2X 功能描述:FPGA - 现场可编程门阵列 CPLD - APEX 20K 2560 Macros 1.8 V RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
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