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参数资料
| 型号： | EP20K1000EFC1020-3 |
| 元件分类： | 数字电位计 |
| 英文描述： | Quad Digital Controlled Potentiometers (XDCP™); Low Noise, Low Power, I2C® Bus, 256 Taps; Temperature Range: -40°C to 85°C; Package: 10-MSOP |
| 中文描述： | FPGA的 |
| 文件页数： | 93/114页 |
| 文件大小： | 1623K |
| 代理商： | EP20K1000EFC1020-3 |
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Altera Corporation
APEX 20K Programmable Logic Device Family Data Sheet
All APEX 20K devices are reconfigurable and are 100% tested prior to
shipment. As a result, test vectors do not have to be generated for fault
coverage purposes. Instead, the designer can focus on simulation and
design verification. In addition, the designer does not need to manage
inventories of different application-specific integrated circuit (ASIC)
designs; APEX 20K devices can be configured on the board for the specific
functionality required.
APEX 20K devices are configured at system power-up with data stored in
an Altera serial configuration device or provided by a system controller.
Altera offers in-system programmability (ISP)-capable EPC1, EPC2, and
EPC16 configuration devices, which configure APEX 20K devices via a
serial data stream. Moreover, APEX 20K devices contain an optimized
interface that permits microprocessors to configure APEX 20K devices
serially or in parallel, and synchronously or asynchronously. The interface
also enables microprocessors to treat APEX 20K devices as memory and
configure the device by writing to a virtual memory location, making
reconfiguration easy.
After an APEX 20K device has been configured, it can be reconfigured
in-circuit by resetting the device and loading new data. Real-time changes
can be made during system operation, enabling innovative reconfigurable
computing applications.
APEX 20K devices are supported by the Altera Quartus II development
system, a single, integrated package that offers HDL and schematic design
entry, compilation and logic synthesis, full simulation and worst-case
timing analysis, SignalTap logic analysis, and device configuration. The
Quartus II software runs on Windows-based PCs, Sun SPARCstations,
and HP 9000 Series 700/800 workstations.
The Quartus II software provides NativeLink interfaces to other industry-
standard PC- and UNIX workstation-based EDA tools. For example,
designers can invoke the Quartus II software from within third-party
design tools. Further, the Quartus II software contains built-in optimized
synthesis libraries; synthesis tools can use these libraries to optimize
designs for APEX 20K devices. For example, the Synopsys Design
Compiler library, supplied with the Quartus II development system,
includes DesignWare functions optimized for the APEX 20K architecture.
相关PDF资料 |
PDF描述 |
|---|---|
| EP20K1000EFC1020-3ES | FPGA |
| EP20K1000EFC672-1ES | FPGA |
| EP20K1000EFC672-2ES | FPGA |
| EP20K1000EFC672-3ES | FPGA |
| EP20K1000EFI1020-1 | 600mA Low Quiescent Current 1.6MHz High Efficiency Synchronous Buck Regulator; Temperature Range: -40°C to 85°C; Package: 8-DFN T&R |
相关代理商/技术参数 |
参数描述 |
|---|---|
| EP20K1000EFC1020-3ES | 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA |
| EP20K1000EFC33-1 | 功能描述:FPGA - 现场可编程门阵列 CPLD - APEX 20K 2560 Macros 1.8 V RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EP20K1000EFC33-1X | 功能描述:FPGA - 现场可编程门阵列 CPLD - APEX 20K 2560 Macros 1.8 V RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EP20K1000EFC33-2 | 功能描述:FPGA - 现场可编程门阵列 CPLD - APEX 20K 2560 Macros 1.8 V RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EP20K1000EFC33-2X | 功能描述:FPGA - 现场可编程门阵列 CPLD - APEX 20K 2560 Macros 1.8 V RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
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