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Altera Corporation
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Preliminary Information
APEX 20K Programmable Logic Device Family Data Sheet
s
Advanced interconnect structure
–
Four-level hierarchical FastTrack Interconnect structure
providing fast, predictable interconnect delays
–
Dedicated carry chain that implements arithmetic functions such
as fast adders, counters, and comparators (automatically used by
software tools and megafunctions)
–
Dedicated cascade chain that implements high-speed,
high-fan-in logic functions (automatically used by software tools
and megafunctions)
–
Interleaved local interconnect allows one LE to drive 29 other
LEs through the fast local interconnect
s
Advanced packaging options
–
Available in a variety of packages with 144 to 984 pins (see
–
FineLine BGATM packages maximize board space efficiency
–
SameFrameTM pin migration providing migration capability
across device densities and package sizes
s
Advanced software support
–
Software design support and automatic place-and-route
provided by the Altera QuartusTM development system for
Windows-based PCs, Sun SPARCstations, and HP 9000
Series 700/800 workstations
–
Altera MegaCoreTM functions and Altera Megafunction Partners
Program (AMPPSM) megafunctions
–
NativeLinkTM integration with popular synthesis, simulation,
and timing analysis tools
–
Quartus SignalTapTM embedded logic analyzer simplifying
in-system design evaluation by giving access to internal nodes
during device operation
Table 3. APEX 20K QFP, BGA & PGA Package Options & I/O Count
Device
144-Pin
TQFP
208-Pin
PQFP
RQFP
240-Pin
PQFP
RQFP
356-Pin
BGA
652-Pin
BGA
655-Pin
PGA
984-Pin
PGA
EP20K100
101
159
189
252
EP20K100E
92
149
181
v
EP20K160E
84
141
173
v
EP20K200
144
174
v
EP20K200E
134
166
v
EP20K300E
118
150
v
EP20K400
502
EP20K400E
100
132
v
EP20K600E
v
EP20K1000E
v