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| 型号： | EP20K100EFC400-2 |
| 厂商： | ALTERA CORP |
| 元件分类： | PLD |
| 英文描述： | LOADABLE PLD, PBGA400 |
| 文件页数： | 38/65页 |
| 文件大小： | 781K |
| 代理商： | EP20K100EFC400-2 |
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Altera Corporation
65
Preliminary Information
APEX 20K Programmable Logic Device Family Data Sheet
Figure 29. APEX 20KE I/O Blocks
Power Sequencing & Hot Socketing
Because APEX 20K devices can be used in a mixed-voltage environment,
they have been designed specifically to tolerate any possible power-up
sequence. Therefore, the VCCIO and VCCINT power planes may be
powered in any order.
Signals can be driven into APEX 20K devices before and during power up
without damaging the device. In addition, APEX 20K devices do not drive
out during power up. Once operating conditions are reached and the
device is configured, APEX 20K devices operate as specified by the user.
SameFrame
Pin-Outs
APEX 20K devices support the SameFrame pin-out feature for
FineLine BGA packages. The SameFrame pin-out feature is the
arrangement of balls on FineLine BGA packages such that the lower-ball-
count packages form a subset of the higher-ball-count packages.
SameFrame pin-outs provide the flexibility to migrate not only from
device to device within the same package, but also from one package to
another. A given printed circuit board (PCB) layout can support multiple
device density/package combinations. For example, a single board layout
can support a range of devices from an EP20K100 device in a 324-pin
FineLine BGA package to an EP20K400 device in a 672-pin
FineLine BGA package.
I/O Blocks
LVDS Output
Block or I/O
Block
LVDS Input
Block or I/O
Block
I/O Blocks
相关PDF资料 |
PDF描述 |
|---|---|
| EP20K100EFC400-3 | LOADABLE PLD, PBGA400 |
| EP20K100EFI400-1 | LOADABLE PLD, PBGA400 |
| EP20K100EFI400-2 | LOADABLE PLD, PBGA400 |
| EP20K100EFI400-3 | LOADABLE PLD, PBGA400 |
| EP20K100EFC784-1 | LOADABLE PLD, PBGA784 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| EP20K100EFI144-1ES | 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA |
| EP20K100EFI144-2ES | 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA |
| EP20K100EFI144-2X | 功能描述:FPGA - 现场可编程门阵列 CPLD - APEX 20K 416 Macro 93 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EP20K100EFI144-3ES | 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA |
| EP20K100EFI324-1ES | 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA |
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