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| 型号： | EP20K100EFC400-2 |
| 厂商： | ALTERA CORP |
| 元件分类： | PLD |
| 英文描述： | LOADABLE PLD, PBGA400 |
| 文件页数： | 30/65页 |
| 文件大小： | 781K |
| 代理商： | EP20K100EFC400-2 |
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Altera Corporation
APEX 20K Programmable Logic Device Family Data Sheet
Preliminary Information
An ESB is fed by the local interconnect, which is driven by adjacent LEs
(for high-speed connection to the ESB) or the MegaLAB interconnect. The
ESB can drive the local, MegaLAB, or FastTrack Interconnect routing
structure to drive LEs and IOEs in the same MegaLAB structure or
anywhere in the device.
Implementing Logic in ROM
In addition to implementing logic with product terms, the ESB can
implement logic functions when it is programmed with a read-only
pattern during configuration, creating a large LUT. With LUTs,
combinatorial functions are implemented by looking up the results, rather
than by computing them. This implementation of combinatorial functions
can be faster than using algorithms implemented in general logic, a
performance advantage that is further enhanced by the fast access times
of ESBs. The large capacity of ESBs enables designers to implement
complex functions in one logic level without the routing delays associated
with linked LEs or distributed RAM blocks. Parameterized functions such
as LPM functions can take advantage of the ESB automatically. Further,
the Quartus software can implement portions of a design with ESBs
where appropriate.
Programmable Speed/Power Control
APEX 20K ESBs offer a high-speed mode that supports very fast operation
on an ESB-by-ESB basis. When high speed is not required, this feature can
be turned off to reduce the ESB’s power dissipation by up to 50%. ESBs
that run at low power incur a nominal timing delay adder. This
Turbo BitTM option is available for ESBs that implement product-term
logic or memory functions. An ESB that is not used will be powered down
so it does not consume DC current.
Designers can program each ESB in the APEX 20K device for either
high-speed or low-power operation. As a result, speed-critical paths in the
design can run at high speed, while the remaining paths operate at
reduced power.
I/O Structure
The APEX 20K I/O element (IOE) contains a bidirectional I/O buffer and
a register that can be used either as an input register for external data
requiring fast setup times, or as an output register for data requiring fast
clock-to-output performance. IOEs can be used as input, output, or
bidirectional pins. The Quartus Compiler uses the programmable
inversion option to invert signals from the row and column interconnect
automatically where appropriate. Because the APEX 20K IOE offers one
output enable per pin, the Quartus Compiler can emulate open-drain
operation efficiently.
相关PDF资料 |
PDF描述 |
|---|---|
| EP20K100EFC400-3 | LOADABLE PLD, PBGA400 |
| EP20K100EFI400-1 | LOADABLE PLD, PBGA400 |
| EP20K100EFI400-2 | LOADABLE PLD, PBGA400 |
| EP20K100EFI400-3 | LOADABLE PLD, PBGA400 |
| EP20K100EFC784-1 | LOADABLE PLD, PBGA784 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| EP20K100EFI144-1ES | 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA |
| EP20K100EFI144-2ES | 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA |
| EP20K100EFI144-2X | 功能描述:FPGA - 现场可编程门阵列 CPLD - APEX 20K 416 Macro 93 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EP20K100EFI144-3ES | 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA |
| EP20K100EFI324-1ES | 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA |
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