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| 型号： | EP20K100EFC400-2 |
| 厂商： | ALTERA CORP |
| 元件分类： | PLD |
| 英文描述： | LOADABLE PLD, PBGA400 |
| 文件页数： | 57/65页 |
| 文件大小： | 781K |
| 代理商： | EP20K100EFC400-2 |
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82
Altera Corporation
APEX 20K Programmable Logic Device Family Data Sheet
Preliminary Information
Notes:
(1)
This parameter is measured without use of the ClockLock or ClockBoost circuits.
(2)
This parameter is measured with use of the ClockLock or ClockBoost circuits.
Power
Consumption
Detailed power consumption information for APEX 20K devices will be
released as it is available.
Conguration &
Operation
The APEX 20K architecture supports several configuration schemes. This
section summarizes the device operating modes and available device
configuration schemes.
Operating Modes
The APEX architecture uses SRAM configuration elements that require
configuration data to be loaded each time the circuit powers up. The
process of physically loading the SRAM data into the device is called
configuration. During initialization, which occurs immediately after
configuration, the device resets registers, enables I/O pins, and begins to
operate as a logic device. The I/O pins are tri-stated during power-up,
and before and during configuration. Together, the configuration and
initialization processes are called command mode; normal device operation
is called user mode.
Before and during device configuration all I/Os are pulled to VCCIO by a
built-in weak pull-up resistor.
Table 26. EP20K400 External Bidirectional Timing Parameters
Symbol
-1 Speed Grade
-2 Speed Grade
-3 Speed Grade
Unit
Min
Max
Min
Max
Min
Max
tINSUBIDIR (1)
1.2
1.5
1.8
ns
tINHBIDIR (1)
0.0
ns
tOUTCOBIDIR (1)
2.0
4.0
2.0
4.1
2.0
5.5
ns
tXZBIDIR (1)
4.9
5.8
6.9
ns
tZXBIDIR (1)
6.0
7.1
8.4
ns
tINSUBIDIR (2)
1.2
1.5
1.8
ns
tINHBIDIR (2)
0.0
ns
tOUTCOBIDIR (2)
0.5
3.0
0.5
3.1
0.5
4.5
ns
tXZBIDIR (2)
3.9
4.8
5.9
ns
tZXBIDIR (2)
5.0
6.1
7.4
ns
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相关代理商/技术参数 |
参数描述 |
|---|---|
| EP20K100EFI144-1ES | 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA |
| EP20K100EFI144-2ES | 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA |
| EP20K100EFI144-2X | 功能描述:FPGA - 现场可编程门阵列 CPLD - APEX 20K 416 Macro 93 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EP20K100EFI144-3ES | 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA |
| EP20K100EFI324-1ES | 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA |
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