参数资料
型号: EP20K100ERC208-1ES
元件分类: 数字电位计
英文描述: Digitally Controlled Potentiometer (XDCP™) Terminal Voltage ±2.7V or ±5V, 128 Taps I2C Serial Interface; Temperature Range: -40°C to 85°C; Package: 10-MSOP
中文描述: FPGA的
文件页数: 38/114页
文件大小: 1623K
代理商: EP20K100ERC208-1ES
Altera Corporation
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APEX 20K Programmable Logic Device Family Data Sheet
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Flexible clock management circuitry with up to four phase-locked
loops (PLLs)
Built-in low-skew clock tree
Up to eight global clock signals
ClockLockTM feature reducing clock delay and skew
ClockBoostTM feature providing clock multiplication and
division
ClockShiftTM programmable clock phase and delay shifting
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Powerful I/O features
Compliant with peripheral component interconnect Special
Interest Group (PCI SIG) PCI Local Bus Specification,
Revision 2.2
for 3.3-V operation at 33 or 66 MHz and 32 or 64 bits
Support for high-speed external memories, including DDR
SDRAM and ZBT SRAM (ZBT is a trademark of Integrated
Device Technology, Inc.)
Bidirectional I/O performance (tCO + tSU) up to 250 MHz
LVDS performance up to 840 Mbits per channel
Direct connection from I/O pins to local interconnect providing
fast tCO and tSU times for complex logic
MultiVolt I/O interface support to interface with 1.8-V, 2.5-V,
3.3-V, and 5.0-V devices (see Table 3)
Programmable clamp to VCCIO
Individual tri-state output enable control for each pin
Programmable output slew-rate control to reduce switching
noise
Support for advanced I/O standards, including low-voltage
differential signaling (LVDS), LVPECL, PCI-X, AGP, CTT, stub-
series terminated logic (SSTL-3 and SSTL-2), Gunning
transceiver logic plus (GTL+), and high-speed terminated logic
(HSTL Class I)
Pull-up on I/O pins before and during configuration
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Advanced interconnect structure
Four-level hierarchical FastTrack Interconnect structure
providing fast, predictable interconnect delays
Dedicated carry chain that implements arithmetic functions such
as fast adders, counters, and comparators (automatically used by
software tools and megafunctions)
Dedicated cascade chain that implements high-speed,
high-fan-in logic functions (automatically used by software tools
and megafunctions)
Interleaved local interconnect allows one LE to drive 29 other
LEs through the fast local interconnect
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Advanced packaging options
Available in a variety of packages with 144 to 1,020 pins (see
Tables 4 through 7)
FineLine BGATM packages maximize board space efficiency
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Advanced software support
Software design support and automatic place-and-route
provided by the Altera QuartusTM II development system for
相关PDF资料
PDF描述
EP20K100ERC208-2ES Digitally Controlled Potentiometer (XDCP™) Terminal Voltage ±2.7V or ±5V, 128 Taps I2C Serial Interface; Temperature Range: -40°C to 85°C; Package: 10-MSOP T&R
EP20K100ERC208-3ES Single Digitally Controlled Potentiometer (XDCP™); Temperature Range: -40°C to 85°C; Package: 8-DFN
EP20K100ETI144-2ES 600kHz/1.2MHz PWM Step-Up Regulator; Temperature Range: -40°C to 85°C; Package: 8-MSOP T&R
EP20K100ETI144-3ES FPGA
EP20K100FC324-1 Field Programmable Gate Array (FPGA)
相关代理商/技术参数
参数描述
EP20K100ERC208-2ES 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA
EP20K100ERC208-3ES 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA
EP20K100ERC240-1ES 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA
EP20K100ERC240-2ES 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA
EP20K100ERC240-3ES 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA