参数资料
型号: EP20K100ERC208-1ES
元件分类: 数字电位计
英文描述: Digitally Controlled Potentiometer (XDCP™) Terminal Voltage ±2.7V or ±5V, 128 Taps I2C Serial Interface; Temperature Range: -40°C to 85°C; Package: 10-MSOP
中文描述: FPGA的
文件页数: 52/114页
文件大小: 1623K
代理商: EP20K100ERC208-1ES
42
Altera Corporation
APEX 20K Programmable Logic Device Family Data Sheet
Each IOE drives a row, column, MegaLAB, or local interconnect when
used as an input or bidirectional pin. A row IOE can drive a local,
MegaLAB, row, and column interconnect; a column IOE can drive the
column interconnect. Figure 27 shows how a row IOE connects to the
interconnect.
Figure 27. Row IOE Connection to the Interconnect
Row Interconnect
MegaLAB Interconnect
Any LE can drive a
pin through the row,
column, and MegaLAB
interconnect.
An LE can drive a pin through the
local interconnect for faster
clock-to-output times.
IOE
Each IOE can drive local,
MegaLAB, row, and column
interconnect. Each IOE data
and OE signal is driven by
the local interconnect.
LAB
相关PDF资料
PDF描述
EP20K100ERC208-2ES Digitally Controlled Potentiometer (XDCP™) Terminal Voltage ±2.7V or ±5V, 128 Taps I2C Serial Interface; Temperature Range: -40°C to 85°C; Package: 10-MSOP T&R
EP20K100ERC208-3ES Single Digitally Controlled Potentiometer (XDCP™); Temperature Range: -40°C to 85°C; Package: 8-DFN
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EP20K100ERC208-2ES 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA
EP20K100ERC208-3ES 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA
EP20K100ERC240-1ES 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA
EP20K100ERC240-2ES 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA
EP20K100ERC240-3ES 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA