- 您现在的位置：买卖IC网 > PDF目录97917 > EP20K200CB652C8 5V, Byte Alterable EEPROM; Temperature Range: -55°C to 125°C; Package: 32-PLCC PDF资料下载
参数资料
| 型号： | EP20K200CB652C8 |
| 英文描述： | 5V, Byte Alterable EEPROM; Temperature Range: -55°C to 125°C; Package: 32-PLCC |
| 中文描述： | 专用集成电路 |
| 文件页数： | 58/114页 |
| 文件大小： | 1623K |
| 代理商： | EP20K200CB652C8 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页当前第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页
48
Altera Corporation
APEX 20K Programmable Logic Device Family Data Sheet
For designs that require both a multiplied and non-multiplied clock, the
clock trace on the board can be connected to CLK2p. Table 14 shows the
combinations supported by the ClockLock and ClockBoost circuitry. The
CLK2p
pin can feed both the ClockLock and ClockBoost circuitry in the
APEX 20K device. However, when both circuits are used, the other clock
pin (CLK1p) cannot be used.
APEX 20KE ClockLock Feature
APEX 20KE devices include an enhanced ClockLock feature set. These
devices include up to four PLLs, which can be used independently. Two
PLLs are designed for either general-purpose use or LVDS use (on devices
that support LVDS I/O pins). The remaining two PLLs are designed for
general-purpose use. The EP20K200E and smaller devices have two PLLs;
the EP20K300E and larger devices have four PLLs.
The following sections describe some of the features offered by the
APEX 20KE PLLs.
External PLL Feedback
The ClockLock circuit’s output can be driven off-chip to clock other
devices in the system; further, the feedback loop of the PLL can be routed
off-chip. This feature allows the designer to exercise fine control over the
I/O interface between the APEX 20KE device and another high-speed
device, such as SDRAM.
Clock Multiplication
The APEX 20KE ClockBoost circuit can multiply or divide clocks by a
programmable number. The clock can be multiplied by m/(n
× k) or
m/(n
× v), where m and k range from 2 to 160, and n and vrange from 1 to
16. Clock multiplication and division can be used for time-domain
multiplexing and other functions, which can reduce design LE
requirements.
Table 14. Multiplication Factor Combinations
Clock 1
Clock 2
×1
×1, ×2
×2
×1, ×2, ×4
×4
相关PDF资料 |
PDF描述 |
|---|---|
| EP20K200CB652C9 | ASIC |
| EP20K200CB652I7 | 5V, Byte Alterable EEPROM; Temperature Range: 0°C to 70°C; Package: 32-PLCC |
| EP20K200CB652I8 | 256K, 32K x 8 Bit; 5 Volt, Byte Alterable EEPROM; Temperature Range: 0°C to 70°C; Package: 28-CerDIP |
| EP20K200CB652I9 | 256K, 32K x 8 Bit; 5 Volt, Byte Alterable EEPROM; Temperature Range: -40°C to 85°C; Package: 28-CerDIP |
| EP20K200CP208C9 | ASIC |
相关代理商/技术参数 |
参数描述 |
|---|---|
| EP20K200CB652C9 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:ASIC |
| EP20K200CB652I7 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:ASIC |
| EP20K200CB652I8 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:ASIC |
| EP20K200CB652I9 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:ASIC |
| EP20K200CF484C7 | 制造商:Altera Corporation 功能描述:IC APEX 20KC FPGA 484FBGA 制造商:Altera Corporation 功能描述:IC FPGA 376 I/O 484FBGA |
发布紧急采购，3分钟左右您将得到回复。