参数资料
型号: EP20K200CB652C8
英文描述: 5V, Byte Alterable EEPROM; Temperature Range: -55°C to 125°C; Package: 32-PLCC
中文描述: 专用集成电路
文件页数: 88/114页
文件大小: 1623K
代理商: EP20K200CB652C8
Altera Corporation
75
APEX 20K Programmable Logic Device Family Data Sheet
Figure 40. Synchronous Bidirectional Pin External Timing
Notes:
(1)
The output enable and input registers are LE registers in the LAB adjacent to a bi-
directional row pin. The output enable register is set with “Output Enable Routing=
Signal-Pin” option in the Quartus II software.
(2)
The LAB adjacent input register is set with “Decrease Input Delay to Internal Cells=
Off”. This maintains a zero hold time for lab adjacent registers while giving a fast,
position independent setup time. A faster setup time with zero hold time is possible
by setting “Decrease Input Delay to Internal Cells= ON” and moving the input
register farther away from the bi-directional pin. The exact position where zero
hold occurs with the minimum setup time, varies with device density and speed
grade.
Table 35 describes the fMAX timing parameters shown in Figure 36.
PRN
CLRN
DQ
PRN
CLRN
DQ
(1)
IOE Register
Bidirectional Pin
Dedicated
Clock
PRN
CLRN
DQ
(1)
XZBIDIR
t
ZXBIDIR
t
OUTCOBIDIR
t
INSUBIDIR
t
INHBIDIR
t
OE Register
Output IOE Register
Input Register
(2)
Table 35. APEX 20K fMAX Timing Parameters
(Part 1 of 2)
Symbol
Parameter
tSU
LE register setup time before clock
tH
LE register hold time after clock
tCO
LE register clock-to-output delay
tLUT
LUT delay for data-in
tESBRC
ESB Asynchronous read cycle time
tESBWC
ESB Asynchronous write cycle time
tESBWESU
ESB WE setup time before clock when using input register
tESBDATASU
ESB data setup time before clock when using input register
tESBADDRSU
ESB address setup time before clock when using input registers
tESBDATACO1
ESB clock-to-output delay when using output registers
tESBDATACO2
ESB clock-to-output delay without output registers
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