参数资料
型号: EP20K200EFI484-2X
厂商: Altera
文件页数: 56/117页
文件大小: 0K
描述: IC APEX 20KE FPGA 200K 484-FBGA
产品培训模块: Three Reasons to Use FPGA's in Industrial Designs
标准包装: 60
系列: APEX-20K®
LAB/CLB数: 832
逻辑元件/单元数: 8320
RAM 位总计: 106496
输入/输出数: 376
门数: 404000
电源电压: 1.71 V ~ 1.89 V
安装类型: 表面贴装
工作温度: -40°C ~ 100°C
封装/外壳: 484-BGA
供应商设备封装: 484-FBGA(23x23)
其它名称: 544-2093
Altera Corporation
43
APEX 20K Programmable Logic Device Family Data Sheet
Figure 28 shows how a column IOE connects to the interconnect.
Figure 28. Column IOE Connection to the Interconnect
Dedicated Fast I/O Pins
APEX 20KE devices incorporate an enhancement to support bidirectional
pins with high internal fanout such as PCI control signals. These pins are
called Dedicated Fast I/O pins (FAST1, FAST2, FAST3, and FAST4) and
replace dedicated inputs. These pins can be used for fast clock, clear, or
high fanout logic signal distribution. They also can drive out. The
Dedicated Fast I/O pin data output and tri-state control are driven by
local interconnect from the adjacent MegaLAB for high speed.
Row Interconnect
Column Interconnect
Each IOE can drive column interconnect. In APEX 20KE devices,
IOEs can also drive FastRow interconnect. Each IOE data
and OE signal is driven by local interconnect.
Any LE or ESB can drive
a column pin through a
row, column, and MegaLAB
interconnect.
IOE
LAB
An LE or ESB can drive a
pin through a local
interconnect for faster
clock-to-output times.
MegaLAB Interconnect
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