参数资料
型号: EP20K400FI672-3
英文描述: Field Programmable Gate Array (FPGA)
中文描述: 现场可编程门阵列(FPGA)
文件页数: 34/114页
文件大小: 1623K
代理商: EP20K400FI672-3
26
Altera Corporation
APEX 20K Programmable Logic Device Family Data Sheet
Figure 13. Product-Term Logic in ESB
Note:
(1)
APEX 20KE devices have four dedicated clocks.
Macrocells
APEX 20K macrocells can be configured individually for either sequential
or combinatorial logic operation. The macrocell consists of three
functional blocks: the logic array, the product-term select matrix, and the
programmable register.
Combinatorial logic is implemented in the product terms. The product-
term select matrix allocates these product terms for use as either primary
logic inputs (to the OR and XOR gates) to implement combinatorial
functions, or as parallel expanders to be used to increase the logic
available to another macrocell. One product term can be inverted; the
Quartus II software uses this feature to perform DeMorgan’s inversion for
more efficient implementation of wide OR functions. The Quartus II
software Compiler can use a NOT-gate push-back technique to emulate an
asynchronous preset. Figure 14 shows the APEX 20K macrocell.
Global Signals
Dedicated Clocks
Macrocell
Inputs (1-16)
CLK[1..0]
ENA[1..0]
CLRN[1..0]
From
Adjacent
LAB
MegaLAB Interconnect
To Row
and Column
Interconnect
2
16
32
2
4
2 or 4
(1)
65
Local
Interconnect
9
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相关代理商/技术参数
参数描述
EP20K400FI672-3ES 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA
EP20K400GC655-1ES 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA
EP20K400GC655-2 制造商:Rochester Electronics LLC 功能描述:- Bulk
EP20K400GC655-2ES 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA
EP20K400GC655-3 制造商:Rochester Electronics LLC 功能描述:- Bulk