参数资料
型号: EP20K400FI672-3
英文描述: Field Programmable Gate Array (FPGA)
中文描述: 现场可编程门阵列(FPGA)
文件页数: 52/114页
文件大小: 1623K
代理商: EP20K400FI672-3
42
Altera Corporation
APEX 20K Programmable Logic Device Family Data Sheet
Each IOE drives a row, column, MegaLAB, or local interconnect when
used as an input or bidirectional pin. A row IOE can drive a local,
MegaLAB, row, and column interconnect; a column IOE can drive the
column interconnect. Figure 27 shows how a row IOE connects to the
interconnect.
Figure 27. Row IOE Connection to the Interconnect
Row Interconnect
MegaLAB Interconnect
Any LE can drive a
pin through the row,
column, and MegaLAB
interconnect.
An LE can drive a pin through the
local interconnect for faster
clock-to-output times.
IOE
Each IOE can drive local,
MegaLAB, row, and column
interconnect. Each IOE data
and OE signal is driven by
the local interconnect.
LAB
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相关代理商/技术参数
参数描述
EP20K400FI672-3ES 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA
EP20K400GC655-1ES 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA
EP20K400GC655-2 制造商:Rochester Electronics LLC 功能描述:- Bulk
EP20K400GC655-2ES 制造商:未知厂家 制造商全称:未知厂家 功能描述:FPGA
EP20K400GC655-3 制造商:Rochester Electronics LLC 功能描述:- Bulk