参数资料
型号: EP9307-CRZR
厂商: Cirrus Logic Inc
文件页数: 10/16页
文件大小: 0K
描述: IC ARM920T 200MHZ PROC 272 TFBGA
标准包装: 500
系列: EP9
核心处理器: ARM9
芯体尺寸: 16/32-位
速度: 200MHz
连通性: EBI/EMI,以太网,I²C,IrDA,键盘/触摸屏,SPI,UART/USART,USB
外围设备: AC'97,DMA,I²S,LCD,LED,MaverickKey,POR,PWM,WDT
输入/输出数: 14
程序存储器类型: ROMless
RAM 容量: 32K x 8
电压 - 电源 (Vcc/Vdd): 1.65 V ~ 3.6 V
数据转换器: A/D 8x12b
振荡器型: 外部
工作温度: 0°C ~ 70°C
封装/外壳: 272-LFBGA
其它名称: Q5809834A
ER667E2B
3
HDLC
Description
When the final byte of a received packet is read into the DMA controller's buffer, the software will be notified
by an HDLC RFC interrupt. However, the DMA controller may not have written the currently buffered part of
the packet to memory, so that the last one to fifteen bytes of a packet may not be accessible.
Workaround
To insure that the DMA channel empties the buffer, do the following (in the HDLC interrupt handler, for
example):
1) Note the values in the MAXCNTx and REMAIN registers for the DMA channel. The difference is the num-
ber of bytes read from the UART/HDLC, which is the size of the HDLC packet. Call this number N. Note
that the BC field of the UART1HDLCRXInfoBuf register should also be N.
2) Temporarily disable the UART DMA RX interface by clearing the RXDMAE bit in the UART1DMACtrl reg-
ister.
3) Wait until the difference between the CURRENTx and BASEx registers in the DMA channel is equal to
N + 1.
At this point, the rest of the packet is guaranteed to have been written to memory. Using this method will
cause an extra byte to be read from the UART by the DMA channel and also written to memory. This last
byte should be ignored.
SDRAM Controller
Description 1
Using the SDRAM controller in auto-precharge mode will produce system instability at external bus speeds
greater than 50MHz.
Workaround
Do not turn on the auto-precharge feature of the SDRAM controller if the external bus speed will be greater
than 50 MHz.
Description 2
When the SDRAM controller is configured for PRECHARGE ALL command, the actual sequence is not
always issued to the SDRAM device(s).
Workaround
Do a read from each SDRAM bank so that a PRECHARGE command is issued to each bank of the SDRAM
device. This will satisfy the required SDRAM initialization sequence.
Due to the effectiveness and simplicity of the software workaround, no silicon fix is planned.
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