参数资料
型号: EP9307-CRZR
厂商: Cirrus Logic Inc
文件页数: 2/16页
文件大小: 0K
描述: IC ARM920T 200MHZ PROC 272 TFBGA
标准包装: 500
系列: EP9
核心处理器: ARM9
芯体尺寸: 16/32-位
速度: 200MHz
连通性: EBI/EMI,以太网,I²C,IrDA,键盘/触摸屏,SPI,UART/USART,USB
外围设备: AC'97,DMA,I²S,LCD,LED,MaverickKey,POR,PWM,WDT
输入/输出数: 14
程序存储器类型: ROMless
RAM 容量: 32K x 8
电压 - 电源 (Vcc/Vdd): 1.65 V ~ 3.6 V
数据转换器: A/D 8x12b
振荡器型: 外部
工作温度: 0°C ~ 70°C
封装/外壳: 272-LFBGA
其它名称: Q5809834A
10
ER667E2B
Workaround
Separating the first and second instruction by one instruction will avoid this error whether or not the
coprocessor is operating in serialized or unserialized mode. For example:
; load sequence
cfadd32ne
c0, c1, c2
; assume this does not execute
nop
; inserted extra instruction here
cfldr64
c3, [r2, #0x0]
; store sequence
cfadd32ne
c4, c5, c6
; assume this does not execute
nop
; inserted extra instruction here
cfstr64
c3, [r2, #0x0]
Note that the effect of branches should also be accounted for, as it is the instruction stream as seen by the
coprocessor that matters, not the order of instructions in the source code. The two instructions following a
taken branch may be seen by the coprocessor and then not executed, and would be treated exactly as the
first instruction above.
To avoid this error when entering exception and interrupt handlers, the first instruction in an interrupt or
exception handler should not be a coprocessor instruction. Since the first instruction is normally a branch,
this error should not appear.
Description 4
When the coprocessor is not in serialized mode2 and forwarding is enabled, memory can be corrupted when
two types of instructions appear in the instruction stream with a particular relative timing.
1) Execute an instruction that is a data operation (not a move between ARM and coprocessor registers)
whose destination is one of the general purpose register c0 through c15.
2) Execute an instruction that is a two-word coprocessor store (either cfstr64 or cfstrd), where the destina-
tion register of the first instruction is the source of the store instruction, that is, the second instruction
stores the result of the first one to memory.
3) Finally, the first and second instruction must appear to the coprocessor with the correct relative timing;
this timing is not simply proportional to the number of intervening instructions and is difficult to predict in
general.
The result is that the lower 32 bits of the result stored to memory will be correct, but the upper the 32 bits
will be wrong. The value appearing in the target register will still be correct.
Workaround
One workaround is to operate the coprocessor without forwarding enabled, with a possible decrease in
performance.
Another is to operate in serialized mode by enabling at least one exception, with significantly reduced
performance.
Another workaround is to insure that at least seven instructions appear between the first and second
instructions that cause the error.
(Continued)
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