- 您现在的位置：买卖IC网 > PDF目录19908 > EPC16QI100 (Altera)IC CONFIG DEVICE 16MBIT 100-PQFP PDF资料下载
参数资料
| 型号： | EPC16QI100 |
| 厂商： | Altera |
| 文件页数： | 35/36页 |
| 文件大小： | 0K |
| 描述： | IC CONFIG DEVICE 16MBIT 100-PQFP |
| 产品培训模块： | Three Reasons to Use FPGA's in Industrial Designs |
| 标准包装： | 66 |
| 系列： | EPC |
| 可编程类型： | 系统内可编程 |
| 存储容量： | 16Mb |
| 电源电压： | 3 V ~ 3.6 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 100-BQFP |
| 供应商设备封装： | 100-PQFP（14x20） |
| 包装： | 托盘 |
| 产品目录页面： | 604 (CN2011-ZH PDF) |
| 其它名称： | 544-1227 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页当前第35页第36页
Page 8
Functional Description
Enhanced Configuration (EPC) Devices Datasheet
January 2012
Altera Corporation
FPGA Configuration
FPGA configuration is managed by the configuration controller chip. This process
includes reading configuration data from the flash memory, decompressing the
configuration data, transmitting configuration data using the appropriate DATA[]
pins, and handling error conditions.
After POR, the controller determines the user-defined configuration options by
reading its option bits from the flash memory. These options include the configuration
scheme, configuration clock speed, decompression, and configuration page settings.
The option bits are stored at flash address location 0x8000 (word address) and occupy
512-bits or 32-words of memory. These options bits are read using the internal flash
interface and the default 10 MHz internal oscillator.
After obtaining the configuration settings, the configuration controller chip checks if
the FPGA is ready to accept configuration data by monitoring the nSTATUS and
CONF
_DONE signals. When the FPGA is ready (nSTATUS is high and CONF_DONE is low),
the controller begins data transfer using the DCLK and DATA[] output pins. The
controller selects the configuration page to be transmitted to the FPGA by sampling
its PGM[2..0] pins after POR or reset.
The function of the configuration unit is to transmit decompressed data to the FPGA,
depending on the configuration scheme. The EPC device supports four concurrent
configuration modes, with n = 1, 2, 4, or 8 (where n is the number of bits that are sent
per DCLK cycle on the DATA[n] signals). The value n = 1 corresponds to the traditional
PS configuration scheme. The values n = 2, 4, and 8 correspond to concurrent
configuration of 2, 4, or 8 different PS configuration chains, respectively. Additionally,
the FPGA can be configured in FPP mode, where eight bits of DATA are clocked into
the FPGA per DCLK cycle. Depending on the configuration bus width (n), the circuit
shifts uncompressed configuration data to the valid DATA[n] pins. Unused DATA[]
pins drive low.
In addition to transmitting configuration data to the FPGAs, the configuration circuit
is also responsible for pausing configuration whenever there is insufficient data
available for transmission. This occurs when the flash read bandwidth is lower than
the configuration write bandwidth. Configuration is paused by stopping the DCLK to
the FPGA, when waiting for data to be read from the flash or for data to be
decompressed. This technique is called “Pausing DCLK”.
The EPC device flash-memories feature a 90-ns access time (approximately 10 MHz).
Hence, the flash read bandwidth is limited to about 160 megabits per second (Mbps)
(16-bit flash data bus, DQ[], at 10 MHz). However, the configuration speeds supported
by Altera FPGAs are much higher and translate to high configuration write
bandwidths. For example, 100-MHz Stratix FPP configuration requires data at the rate
of 800 Mbps (8-bit DATA[] bus at 100 MHz). This is much higher than the 160 Mbps the
flash memory can support and is the limiting factor for configuration time.
Compression increases the effective flash-read bandwidth as the same amount of
configuration data takes up less space in the flash memory after compression. Since
Stratix configuration data compression ratios are approximately two, the effective
read bandwidth doubles to about 320 Mbps.
相关PDF资料 |
PDF描述 |
|---|---|
| LTC4211IS8#TRPBF | IC CONTROLLER HOT SWAP 8-SOIC |
| V48C8H100BL3 | CONVERTER MOD DC/DC 8V 100W |
| AGM22DTAN | CONN EDGECARD 44POS R/A .156 SLD |
| FMC50DRYH-S13 | CONN EDGCARD 100POS .100 EXTEND |
| V48C8H100BL | CONVERTER MOD DC/DC 8V 100W |
相关代理商/技术参数 |
参数描述 |
|---|---|
| EPC16QI100N | 功能描述:FPGA-配置存储器 IC - Ser. Config Mem Flash 16Mb 33 MHz RoHS:否 制造商:Altera Corporation 存储类型:Flash 存储容量:1.6 Mbit 工作频率:10 MHz 电源电压-最大:5.25 V 电源电压-最小:3 V 电源电流:50 uA 最大工作温度:+ 85 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:PLCC-20 |
| EPC16UC88 | 功能描述:FPGA-配置存储器 IC - Ser. Config Mem Flash 16Mb 33 MHz RoHS:否 制造商:Altera Corporation 存储类型:Flash 存储容量:1.6 Mbit 工作频率:10 MHz 电源电压-最大:5.25 V 电源电压-最小:3 V 电源电流:50 uA 最大工作温度:+ 85 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:PLCC-20 |
| EPC16UC88AA | 功能描述:IC CONFIG DEVICE 16MBIT 88-UBGA RoHS:否 类别:集成电路 (IC) >> 存储器 - 用于 FPGA 的配置 Proms 系列:EPC 产品变化通告:Product Discontinuation 28/Jul/2010 标准包装:98 系列:- 可编程类型:OTP 存储容量:300kb 电源电压:3 V ~ 3.6 V 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 供应商设备封装:8-TSOP 包装:管件 |
| EPC16UC88N | 功能描述:FPGA-配置存储器 IC - Ser. Config Mem Flash 16Mb 33 MHz RoHS:否 制造商:Altera Corporation 存储类型:Flash 存储容量:1.6 Mbit 工作频率:10 MHz 电源电压-最大:5.25 V 电源电压-最小:3 V 电源电流:50 uA 最大工作温度:+ 85 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:PLCC-20 |
| EPC16UI88AA | 功能描述:FPGA-配置存储器 IC - Ser. Config Mem Flash 16Mb 33 MHz RoHS:否 制造商:Altera Corporation 存储类型:Flash 存储容量:1.6 Mbit 工作频率:10 MHz 电源电压-最大:5.25 V 电源电压-最小:3 V 电源电流:50 uA 最大工作温度:+ 85 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:PLCC-20 |
发布紧急采购，3分钟左右您将得到回复。