参数资料
型号: EPCS1SI8
厂商: Altera
文件页数: 30/40页
文件大小: 0K
描述: IC CONFIG DEVICE 1MBIT 8-SOIC
产品培训模块: Three Reasons to Use FPGA's in Industrial Designs
标准包装: 100
系列: EPCS
可编程类型: 系统内可编程
存储容量: 1Mb
电源电压: 3 V ~ 3.6 V
工作温度: -40°C ~ 85°C
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
供应商设备封装: 8-SOIC
包装: 管件
产品目录页面: 604 (CN2011-ZH PDF)
其它名称: 544-1241-5
Page 36
Pin Information
Serial Configuration (EPCS) Devices Datasheet
January 2014
Altera Corporation
Table 23 lists the pin description of the EPCS device.
Figure 23 shows the layout recommendation for vertical migration from the EPCS1
device to the EPCS128 device.
Table 23. EPCS Device Pin Description
Pin
Name
Pin Number
in 8-Pin
SOIC
Package
Pin Number
in 16-Pin
SOIC
Package
Pin Type
Description
DATA
2
8
Output
The DATA output signal transfers data serially out of the EPCS device
to the FPGA during the read operation or configuration. During the
read operation or configuration, the EPCS device is enabled by pulling
the nCS signal low. The DATA signal transitions on the falling edge of
the DCLK signal.
ASDI
5
15
Input
The ASDI signal is used to transfer data serially into the EPCS device.
This pin are also receiving data that are programmed into the EPCS
device. Data is latched on the rising edge of the DCLK signal.
nCS
1
7
Input
The nCS signal toggles at the beginning and the end of a valid
instruction. When this signal goes high, the device is deselected and
the DATA pin is tri-stated. When this signal goes low, the device is
enabled and in an active mode. After power up, the EPCS device
requires a falling edge on the nCS signal before the EPCS device
begins any operation.
DCLK
6
16
Input
The FPGA provides the DCLK signal. This signal provides the timing
for the serial interface. The data presented on the ASDI pin is latched
to the EPCS device on the rising edge of the DCLK signal. The data on
the DATA pin changes after the falling edge of the DCLK signal and is
latched into the FPGA on the next falling edge of the DCLK signal.
VCC
3, 7, 8
1, 2, 9
Power
Connect the power pins to a 3.3-V power supply.
GND
4
10
GND
Ground pin.
Figure 23. Layout Recommendation for Vertical Migration from the EPCS1 Device to the EPCS128
Device
Pi
n1
ID
Pin 1 ID
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