参数资料
型号: EPCS1SI8
厂商: Altera
文件页数: 6/40页
文件大小: 0K
描述: IC CONFIG DEVICE 1MBIT 8-SOIC
产品培训模块: Three Reasons to Use FPGA's in Industrial Designs
标准包装: 100
系列: EPCS
可编程类型: 系统内可编程
存储容量: 1Mb
电源电压: 3 V ~ 3.6 V
工作温度: -40°C ~ 85°C
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
供应商设备封装: 8-SOIC
包装: 管件
产品目录页面: 604 (CN2011-ZH PDF)
其它名称: 544-1241-5
Page 14
EPCS Device Memory Access
Serial Configuration (EPCS) Devices Datasheet
January 2014
Altera Corporation
Operation Codes
This section describes the operations that you can use to access the memory in EPCS
devices. Use the DATA, DCLK, ASDI, and nCS signals to access the memory in EPCS
devices. When performing the operation, addresses and data are shifted in and out of
the device serially, with MSB first.
The device samples the AS data input on the first rising edge of the DCLK after the
active low chip select (nCS) input signal is driven low. Shift the operation code, with
MSB first, into the EPCS device serially through the AS data input (ASDI) pin. Each
operation code bit is latched into the EPCS device on the rising edge of the DCLK.
Different operations require a different sequence of inputs. While executing an
operation, you must shift in the desired operation code, followed by the address bytes
or data bytes, both address and data bytes, or none of them. The device must drive
nCS
pin high after the last bit of the operation sequence is shifted in. Table 8 lists the
operation sequence for every operation supported by the EPCS devices.
For read operations, the data read is shifted out on the DATA pin. You can drive the nCS
pin high after any bit of the data-out sequence is shifted out.
For write and erase operations, drive the nCS pin high at a byte boundary that is in a
multiple of eight clock pulses. Otherwise, the operation is rejected and not executed.
All attempts to access the memory contents while a write or erase cycle is in progress
are rejected, and the write or erase cycle will continue unaffected.
5
H'140000
H'17FFFF
4
H'100000
H'13FFFF
3
H'0C0000
H'0FFFFF
2
H'080000
H'0BFFFF
1
H'040000
H'07FFFF
0
H'000000
H'03FFFF
Table 7. Address Range for Sectors in EPCS128 Devices (Part 3 of 3)
Sector
Address Range (Byte Addresses in HEX)
Start
End
Table 8. EPCS Devices Operation Codes
Operation
Operation Code (1)
Address Bytes
Dummy Bytes
Data Bytes
DCLK fMAX
(MHz)
Write enable
0000 0110
00
0
25
Write disable
0000 0100
00
0
25
Read status
0000 0101
0
1 to infinite (2)
32
Read bytes
0000 0011
3
0
1 to infinite (2)
20
Read silicon ID (4)
1010 1011
0
3
1 to infinite (2)
32
Fast read
0000 1011
3
1
1 to infinite (2)
40
Write status
0000 0001
00
1
25
Write bytes
0000 0010
3
0
1 to 256 (3)
25
Erase bulk
1100 0111
00
0
25
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