参数资料
型号: EPCS1SI8
厂商: Altera
文件页数: 7/40页
文件大小: 0K
描述: IC CONFIG DEVICE 1MBIT 8-SOIC
产品培训模块: Three Reasons to Use FPGA's in Industrial Designs
标准包装: 100
系列: EPCS
可编程类型: 系统内可编程
存储容量: 1Mb
电源电压: 3 V ~ 3.6 V
工作温度: -40°C ~ 85°C
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
供应商设备封装: 8-SOIC
包装: 管件
产品目录页面: 604 (CN2011-ZH PDF)
其它名称: 544-1241-5
EPCS Device Memory Access
Page 15
Serial Configuration (EPCS) Devices Datasheet
January 2014
Altera Corporation
Write Enable Operation
The write enable operation code is b'0000 0110, and it lists the MSB first. The write
enable operation sets the write enable latch bit, which is bit 1 in the status register.
Always set the write enable latch bit before write bytes, write status, erase bulk, and
erase sector operations. Figure 5 shows the instruction sequence of the write enable
operation.
Write Disable Operation
The write disable operation code is b'0000 0100 and it lists the MSB first. The write
disable operation resets the write enable latch bit, which is bit 1 in the status register.
To prevent the memory from being written unintentionally, the write enable latch bit
is automatically reset when implementing the write disable operation, and under the
following conditions:
Power up
Write bytes operation completion
Write status operation completion
Erase bulk operation completion
Erase sector operation completion
Erase sector
1101 1000
30
0
25
Read device
identification (5)
1001 1111
0
2
1 to infinite (2)
25
Notes to Table 8:
(1) List MSB first and LSB last.
(2) The status register, data, or silicon ID is read out at least once on the DATA pin and is continuously read out until the nCS pin is driven high.
(3) A write bytes operation requires at least one data byte on the DATA pin. If more than 256 bytes are sent to the device, only the last 256 bytes
are written to the memory.
(4) The read silicon ID operation is available only for EPCS1, EPCS4, EPCS16, and EPCS64 devices.
(5) The read device identification operation is available only for EPCS128 devices.
Table 8. EPCS Devices Operation Codes
Operation
Operation Code (1)
Address Bytes
Dummy Bytes
Data Bytes
DCLK fMAX
(MHz)
Figure 5. Write Enable Operation Timing Diagram
nCS
DCLK
ASDI
DATA
01234567
Operation Code
High Impedance
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