参数资料
| 型号： | EPF10K130EQI240-2 |
| 厂商： | Altera |
| 文件页数： | 17/100页 |
| 文件大小： | 0K |
| 描述： | IC FLEX 10KE FPGA 130K 240-PQFP |
| 产品培训模块： | Three Reasons to Use FPGA's in Industrial Designs |
| 标准包装： | 24 |
| 系列： | FLEX-10KE® |
| LAB/CLB数： | 832 |
| 逻辑元件/单元数： | 6656 |
| RAM 位总计： | 65536 |
| 输入/输出数： | 186 |
| 门数： | 342000 |
| 电源电压： | 2.375 V ~ 2.625 V |
| 安装类型： | 表面贴装 |
| 工作温度： | -40°C ~ 100°C |
| 封装/外壳： | 240-BFQFP |
| 供应商设备封装： | 240-PQFP（32x32） |
| 其它名称： | 544-2206 |
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Altera Corporation
23
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
Normal Mode
The normal mode is suitable for general logic applications and wide
decoding functions that can take advantage of a cascade chain. In normal
mode, four data inputs from the LAB local interconnect and the carry-in
are inputs to a four-input LUT. The Altera Compiler automatically selects
the carry-in or the DATA3 signal as one of the inputs to the LUT. The LUT
output can be combined with the cascade-in signal to form a cascade chain
through the cascade-out signal. Either the register or the LUT can be used
to drive both the local interconnect and the FastTrack Interconnect routing
structure at the same time.
The LUT and the register in the LE can be used independently (register
packing). To support register packing, the LE has two outputs; one drives
the local interconnect, and the other drives the FastTrack Interconnect
routing structure. The DATA4 signal can drive the register directly,
allowing the LUT to compute a function that is independent of the
registered signal; a three-input function can be computed in the LUT, and
a fourth independent signal can be registered. Alternatively, a four-input
function can be generated, and one of the inputs to this function can be
used to drive the register. The register in a packed LE can still use the clock
enable, clear, and preset signals in the LE. In a packed LE, the register can
drive the FastTrack Interconnect routing structure while the LUT drives
the local interconnect, or vice versa.
Arithmetic Mode
The arithmetic mode offers 2 three-input LUTs that are ideal for
implementing adders, accumulators, and comparators. One LUT
computes a three-input function; the other generates a carry output. As
two data inputs from the LAB local interconnect to generate a
combinatorial or registered output. For example, in an adder, this output
is the sum of three signals: a, b, and carry-in. The second LUT uses the
same three signals to generate a carry-out signal, thereby creating a carry
chain. The arithmetic mode also supports simultaneous use of the cascade
chain.
Up/Down Counter Mode
The up/down counter mode offers counter enable, clock enable,
synchronous up/down control, and data loading options. These control
signals are generated by the data inputs from the LAB local interconnect,
the carry-in signal, and output feedback from the programmable register.
Use 2 three-input LUTs: one generates the counter data, and the other
generates the fast carry bit. A 2-to-1 multiplexer provides synchronous
loading. Data can also be loaded asynchronously with the clear and preset
register control signals without using the LUT resources.
相关PDF资料 |
PDF描述 |
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| AMC50DREF | CONN EDGECARD 100PS .100 EYELET |
| 170-050-272-000 | CONN DB50 CRIMP FEMALE TIN |
| 170-037-271L010 | CONN DB37 CRIMP FEM YLW CHROME |
| AMC25DRAI | CONN EDGECARD 50POS .100 R/A DIP |
| A14V60A-PQ160C | IC FPGA 6K GATES 3.3V 160-PQFP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| EPF10K130EQI240-2N | 功能描述:FPGA - 现场可编程门阵列 FPGA - Flex 10K 832 LABs 186 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EPF10K130V | 制造商:ALTERA 制造商全称:Altera Corporation 功能描述:Embedded Programmable Logic Device Family |
| EPF10K130VBC600-2 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| EPF10K130VBC600-3 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| EPF10K130VBC600-4 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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