参数资料
| 型号： | EPF10K130EQI240-2 |
| 厂商： | Altera |
| 文件页数： | 37/100页 |
| 文件大小： | 0K |
| 描述： | IC FLEX 10KE FPGA 130K 240-PQFP |
| 产品培训模块： | Three Reasons to Use FPGA's in Industrial Designs |
| 标准包装： | 24 |
| 系列： | FLEX-10KE® |
| LAB/CLB数： | 832 |
| 逻辑元件/单元数： | 6656 |
| RAM 位总计： | 65536 |
| 输入/输出数： | 186 |
| 门数： | 342000 |
| 电源电压： | 2.375 V ~ 2.625 V |
| 安装类型： | 表面贴装 |
| 工作温度： | -40°C ~ 100°C |
| 封装/外壳： | 240-BFQFP |
| 供应商设备封装： | 240-PQFP（32x32） |
| 其它名称： | 544-2206 |
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Altera Corporation
41
FLEX 10KE Embedded Programmable Logic Devices Data Sheet
Notes to tables:
(1)
To implement the ClockLock and ClockBoost circuitry with the MAX+PLUS II software, designers must specify the
input frequency. The Altera software tunes the PLL in the ClockLock and ClockBoost circuitry to this frequency.
The fCLKDEV parameter specifies how much the incoming clock can differ from the specified frequency during
device operation. Simulation does not reflect this parameter.
(2)
Twenty-five thousand parts per million (PPM) equates to 2.5% of input clock period.
(3)
During device configuration, the ClockLock and ClockBoost circuitry is configured before the rest of the device. If
the incoming clock is supplied during configuration, the ClockLock and ClockBoost circuitry locks during
configuration because the tLOCK value is less than the time required for configuration.
(4)
The tJITTER specification is measured under long-term observation. The maximum value for tJITTER is 200 ps if
tINCLKSTB is lower than 50 ps.
I/O
Configuration
This section discusses the peripheral component interconnect (PCI)
pull-up clamping diode option, slew-rate control, open-drain output
option, and MultiVolt I/O interface for FLEX 10KE devices. The PCI
pull-up clamping diode, slew-rate control, and open-drain output options
are controlled pin-by-pin via Altera software logic options. The MultiVolt
I/O interface is controlled by connecting VCCIO to a different voltage than
VCCINT. Its effect can be simulated in the Altera software via the Global
Project Device Options
dialog box (Assign menu).
Table 13. ClockLock & ClockBoost Parameters for -2 Speed-Grade Devices
Symbol
Parameter
Condition
Min
Typ
Max
Unit
tR
Input rise time
5ns
tF
Input fall time
5ns
tINDUTY
Input duty cycle
40
60
%
fCLK1
Input clock frequency (ClockBoost
clock multiplication factor equals 1)
25
75
MHz
fCLK2
Input clock frequency (ClockBoost
clock multiplication factor equals 2)
16
37.5
MHz
fCLKDEV
Input deviation from user
specification in the MAX+PLUS II
software
25,000
PPM
tINCLKSTB
Input clock stability (measured
between adjacent clocks)
100
ps
tLOCK
Time required for ClockLock or
ClockBoost to acquire lock
10
s
tJITTER
Jitter on ClockLock or ClockBoost-
generated clock
t INCLKSTB < 100
250
ps
t INCLKSTB < 50
200
ps
tOUTDUTY
Duty cycle for ClockLock or
ClockBoost-generated clock
40
50
60
%
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相关代理商/技术参数 |
参数描述 |
|---|---|
| EPF10K130EQI240-2N | 功能描述:FPGA - 现场可编程门阵列 FPGA - Flex 10K 832 LABs 186 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| EPF10K130V | 制造商:ALTERA 制造商全称:Altera Corporation 功能描述:Embedded Programmable Logic Device Family |
| EPF10K130VBC600-2 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| EPF10K130VBC600-3 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| EPF10K130VBC600-4 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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